ATtiny1624/1626/1627

DIRCLR

Data Direction Clear

  0x02 8 - 0x00    

Data Direction Clear

Bit  7 6 5 4 3 2 1 0  
  DIRCLR[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – DIRCLR[7:0]: Data Direction Clear

Data Direction Clear

This bit field controls the output driver for each PORTx pin, without using a read-modify-write operation.

Writing a ‘0’ to bit n in this bit field has no effect.

Writing a ‘1’ to bit n in this bit field will clear the corresponding bit in PORTx.DIR, which will configure pin n (Pxn) as an input-only pin and disable the output driver.

Reading this bit field will return the value of PORTx.DIR.