ATtiny1624/1626/1627

LUTnCTRLB

LUT n Control B

Notes:
  1. 1.SPI connections to the CCL work in Host SPI mode only.
  2. 2.USART connections to the CCL work only when the USART is in one of the following modes:
    • Asynchronous USART
    • Synchronous USART host
  0x09 + n*0x04 [n=0..3] 8 Enable-Protected 0x00   4 4 0,1,2,3,4,5,6,7 n

LUT n Control B

Bit  7 6 5 4 3 2 1 0  
  INSEL1[3:0] INSEL0[3:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 3:0 – INSEL0[3:0]: LUT n Input 0 Source Selection

LUT n Input 0 Source Selection

These bits select the source for input 0 of LUT n.

Value Name Description
0x0 MASK Masked input
0x1 FEEDBACK Feedback input
0x2 LINK Output from LUT(n+1) as input source
0x3 EVENTA Event A as input source
0x4 EVENTB Event B as input source
0x5 IO IN0 input source
0x6 AC0 AC0 OUT input source
0x7 - Reserved
0x8 USART0 USART0 TXD input source
0x9 SPI0 SPI0 MOSI input source
0xA TCA0 TCA0 WO0 input source
0xB - Reserved
0xC TCB0 TCB0 WO input source
Other - Reserved

Bits 7:4 – INSEL1[3:0]: LUT n Input 1 Source Selection

LUT n Input 1 Source Selection

These bits select the source for input 1 of LUT n.

Value Name Description
0x0 MASK Masked input
0x1 FEEDBACK Feedback input
0x2 LINK Output from LUT(n+1) as input source
0x3 EVENTA Event A as input source
0x4 EVENTB Event B as input source
0x5 IO IN1 input source
0x6 AC0 AC0 OUT input source
0x7 - Reserved
0x8 USART1 USART1 TXD input source
0x9 SPI0 SPI0 MOSI input source
0xA TCA0 TCA0 WO1 input source
0xB - Reserved
0xC TCB1 TCB1 WO input source
Other - Reserved