Contents

Introduction tinyAVR® 2 Family Overview 2.1. Memory Overview 2.2. Peripheral Overview Features 4. Block Diagram 5. Pinout 5.1. 14-Pin SOIC, TSSOP 5.2. 20-Pin SOIC, SSOP 5.3. 20-Pin VQFN 5.4. 24-Pin VQFN 6. I/O Multiplexing and Considerations 6.1. I/O Multiplexing 7. Hardware Guidelines 7.1. General Guidelines 7.1.1. Special Consideration for Packages with Center Pad 7.2. Connection for Power Supply 7.2.1. Digital Power Supply 7.3. Connection for RESET 7.4. Connection for UPDI Programming 7.5. Connecting External Crystal Oscillators 7.5.1. Connection for XOSC32K (External 32.768 kHz Crystal Oscillator) 7.6. Connection for External Voltage Reference 8. Conventions 8.1. Numerical Notation 8.2. Memory Size and Type 8.3. Frequency and Time 8.4. Registers and Bits 8.4.1. Addressing Registers from Header Files 8.5. ADC Parameter Definitions 9. AVR CPU 9.1. Features 9.2. Overview 9.3. Architecture 9.4. Arithmetic Logic Unit (ALU) 9.4.1. Hardware Multiplier 9.5. Functional Description 9.5.1. Program Flow 9.5.2. Instruction Execution Timing 9.5.3. Status Register 9.5.4. Stack and Stack Pointer 9.5.5. Register File 9.5.5.1. The X-, Y-, and Z-Registers 9.5.6. Configuration Change Protection (CCP) 9.5.6.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 9.5.6.2. Sequence for Execution of Self-Programming 9.5.7. On-Chip Debug Capabilities 9.6. Register Summary 9.7. Register Description 9.7.1. CCP 9.7.2. SP 9.7.3. SREG 10. Memories 10.1. Overview 10.2. Memory Map 10.3. In-System Reprogrammable Flash Program Memory 10.4. SRAM Data Memory 10.5. EEPROM Data Memory 10.6. USERROW - User Row 10.7. LOCKBIT - Memory Sections Access Protection 10.7.1. Lock Bit Summary 10.7.2. Lock Bit Description 10.7.2.1. Lock Bits 10.8. FUSE - Configuration and User Fuses 10.8.1. Fuse Summary 10.8.2. Fuse Description 10.8.2.1. Watchdog Configuration 10.8.2.2. BOD Configuration 10.8.2.3. Oscillator Configuration 10.8.2.4. System Configuration 0 10.8.2.5. System Configuration 1 10.8.2.6. Application Code End 10.8.2.7. Boot End 10.9. SIGROW - Signature Row 10.9.1. Signature Row Summary 10.9.2. Signature Row Description 10.9.2.1. Device ID n 10.9.2.2. Serial Number Byte n 10.9.2.3. OSC16 Calibration Byte 10.9.2.4. OSC16 Temperature Calibration Byte 10.9.2.5. OSC20 Calibration Byte 10.9.2.6. OSC20 Temperature Calibration Byte 10.9.2.7. Temperature Sensor Calibration n 10.10. I/O Memory 10.10.1. Accessing 16-Bit Registers 10.10.2. Accessing 32-Bit Registers 11. Peripherals and Architecture 11.1. Peripheral Address Map 11.2. Interrupt Vector Mapping 11.3. SYSCFG - System Configuration 11.3.1. Register Summary 11.3.2. Register Description 11.3.2.1. Device Revision ID Register 12. General Purpose I/O Registers 12.1. Register Summary 12.2. Register Description 12.2.1. General Purpose I/O Register n 13. NVMCTRL - Nonvolatile Memory Controller 13.1. Features 13.2. Overview 13.2.1. Block Diagram 13.3. Functional Description 13.3.1. Memory Organization 13.3.1.1. Flash 13.3.1.2. EEPROM 13.3.1.3. User Row 13.3.2. Memory Access 13.3.2.1. Read 13.3.2.2. Page Buffer Load 13.3.2.3. Programming 13.3.2.4. Commands 13.3.2.4.1. Write Page Command 13.3.2.4.2. Erase Page Command 13.3.2.4.3. Erase/Write Page Command 13.3.2.4.4. Page Buffer Clear Command 13.3.2.4.5. Chip Erase Command 13.3.2.4.6. EEPROM Erase Command 13.3.2.4.7. Write Fuse Command 13.3.2.5. Write Access after Reset 13.3.3. Preventing Flash/EEPROM Corruption 13.3.4. Interrupts 13.3.5. Sleep Mode Operation 13.3.6. Configuration Change Protection 13.4. Register Summary 13.5. Register Description 13.5.1. Control A 13.5.2. Control B 13.5.3. Status 13.5.4. Interrupt Control 13.5.5. Interrupt Flags 13.5.6. Data 13.5.7. Address 14. CLKCTRL - Clock Controller 14.1. Features 14.2. Overview 14.2.1. Block Diagram - CLKCTRL 14.2.2. Signal Description 14.3. Functional Description 14.3.1. Sleep Mode Operation 14.3.2. Main Clock Selection and Prescaler 14.3.3. Main Clock After Reset 14.3.4. Clock Sources 14.3.4.1. Internal Oscillators 14.3.4.1.1. 20 MHz Oscillator (OSC20M) 14.3.4.1.1.1. OSC20M Stored Frequency Error Compensation 14.3.4.1.2. 32.768 kHz Oscillator (OSCULP32K) 14.3.4.2. External Clock Sources 14.3.4.2.1. 32.768 kHz Crystal Oscillator (XOSC32K) 14.3.4.2.2. External Clock (EXTCLK) 14.3.5. Configuration Change Protection 14.4. Register Summary 14.5. Register Description 14.5.1. Main Clock Control A 14.5.2. Main Clock Control B 14.5.3. Main Clock Lock 14.5.4. Main Clock Status 14.5.5. 20 MHz Oscillator Control A 14.5.6. 20 MHz Oscillator Calibration A 14.5.7. 20 MHz Oscillator Calibration B 14.5.8. 32.768 kHz Oscillator Control A 14.5.9. 32.768 kHz Crystal Oscillator Control A 15. SLPCTRL - Sleep Controller 15.1. Features 15.2. Overview 15.2.1. Block Diagram 15.3. Functional Description 15.3.1. Initialization 15.3.2. Operation 15.3.2.1. Sleep Modes 15.3.2.2. Wake-up Time 15.3.3. Debug Operation 15.4. Register Summary 15.5. Register Description 15.5.1. Control A 16. RSTCTRL - Reset Controller 16.1. Features 16.2. Overview 16.2.1. Block Diagram 16.2.2. Signal Description 16.3. Functional Description 16.3.1. Initialization 16.3.2. Operation 16.3.2.1. Reset Sources 16.3.2.1.1. Power-on Reset (POR) 16.3.2.1.2. Brown-out Detector (BOD) Reset 16.3.2.1.3. External Reset 16.3.2.1.4. Watchdog Reset 16.3.2.1.5. Software Reset 16.3.2.1.6. Unified Program and Debug Interface (UPDI) Reset 16.3.2.1.7. Domains Affected By Reset 16.3.2.2. Reset Time 16.3.3. Sleep Mode Operation 16.3.4. Configuration Change Protection 16.4. Register Summary 16.5. Register Description 16.5.1. Reset Flag Register 16.5.2. Software Reset Register 17. CPUINT - CPU Interrupt Controller 17.1. Features 17.2. Overview 17.2.1. Block Diagram 17.3. Functional Description 17.3.1. Initialization 17.3.2. Operation 17.3.2.1. Enabling, Disabling and Resetting 17.3.2.2. Interrupt Vector Locations 17.3.2.3. Interrupt Response Time 17.3.2.4. Interrupt Priority 17.3.2.4.1. Non-Maskable Interrupts 17.3.2.4.2. High-Priority Interrupt 17.3.2.4.3. Normal-Priority Interrupts 17.3.2.4.3.1. Static Scheduling 17.3.2.4.3.2. Modified Static Scheduling 17.3.2.4.3.3. Round Robin Scheduling 17.3.2.5. Compact Vector Table 17.3.3. Debug Operation 17.3.4. Configuration Change Protection 17.4. Register Summary 17.5. Register Description 17.5.1. Control A 17.5.2. Status 17.5.3. Interrupt Priority Level 0 17.5.4. Interrupt Vector with Priority Level 1 18. EVSYS - Event System 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.2.2. Signal Description 18.3. Functional Description 18.3.1. Initialization 18.3.2. Operation 18.3.2.1. Event User Multiplexer Setup 18.3.2.2. Event System Channel 18.3.2.3. Event Generators 18.3.2.4. Event Users 18.3.2.5. Synchronization 18.3.2.6. Software Event 18.3.3. Sleep Mode Operation 18.3.4. Debug Operation 18.4. Register Summary 18.5. Register Description 18.5.1. Software Events 18.5.2. Channel n Generator Selection 18.5.3. User Channel MUX 19. PORTMUX - Port Multiplexer 19.1. Overview 19.2. Register Summary 19.3. Register Description 19.3.1. EVSYS Pin Position 19.3.2. CCL Pin Position 19.3.3. USART Pin Position 19.3.4. SPI Pin Positions 19.3.5. TCA Pin Positions 19.3.6. TCB Pin Position 20. PORT - I/O Pin Configuration 20.1. Features 20.2. Overview 20.2.1. Block Diagram 20.2.2. Signal Description 20.3. Functional Description 20.3.1. Initialization 20.3.2. Operation 20.3.2.1. Basic Functions 20.3.2.2. Port Configuration 20.3.2.3. Pin Configuration 20.3.2.4. Virtual Ports 20.3.2.5. Peripheral Override 20.3.3. Interrupts 20.3.3.1. Asynchronous Sensing Pin Properties 20.3.4. Events 20.3.5. Sleep Mode Operation 20.3.6. Debug Operation 20.4. Register Summary - PORTx 20.5. Register Description - PORTx 20.5.1. Data Direction 20.5.2. Data Direction Set 20.5.3. Data Direction Clear 20.5.4. Data Direction Toggle 20.5.5. Output Value 20.5.6. Output Value Set 20.5.7. Output Value Clear 20.5.8. Output Value Toggle 20.5.9. Input Value 20.5.10. Interrupt Flags 20.5.11. Port Control 20.5.12. Pin n Control 20.6. Register Summary - VPORTx 20.7. Register Description - VPORTx 20.7.1. Data Direction 20.7.2. Output Value 20.7.3. Input Value 20.7.4. Interrupt Flags 21. BOD - Brown-out Detector 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.3. Functional Description 21.3.1. Initialization 21.3.2. Interrupts 21.3.3. Sleep Mode Operation 21.3.4. Configuration Change Protection 21.4. Register Summary 21.5. Register Description 21.5.1. Control A 21.5.2. Control B 21.5.3. VLM Control A 21.5.4. Interrupt Control 21.5.5. VLM Interrupt Flags 21.5.6. VLM Status 22. VREF - Voltage Reference 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.3. Functional Description 22.3.1. Initialization 22.4. Register Summary 22.5. Register Description 22.5.1. Control A 22.5.2. Control B 23. WDT - Watchdog Timer 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.2.2. Signal Description 23.3. Functional Description 23.3.1. Initialization 23.3.2. Clocks 23.3.3. Operation 23.3.3.1. Normal Mode 23.3.3.2. Window Mode 23.3.3.3. Preventing Unintentional Changes 23.3.4. Sleep Mode Operation 23.3.5. Debug Operation 23.3.6. Synchronization 23.3.7. Configuration Change Protection 23.4. Register Summary 23.5. Register Description 23.5.1. Control A 23.5.2. Status 24. TCA - 16-bit Timer/Counter Type A 24.1. Features 24.2. Overview 24.2.1. Block Diagram 24.2.2. Signal Description 24.3. Functional Description 24.3.1. Definitions 24.3.2. Initialization 24.3.3. Operation 24.3.3.1. Normal Operation 24.3.3.2. Double Buffering 24.3.3.3. Changing the Period 24.3.3.4. Compare Channel 24.3.3.4.1. Waveform Generation 24.3.3.4.2. Frequency (FRQ) Waveform Generation 24.3.3.4.3. Single-Slope PWM Generation 24.3.3.4.4. Dual-Slope PWM 24.3.3.4.5. Port Override for Waveform Generation 24.3.3.5. Timer/Counter Commands 24.3.3.6. Split Mode - Two 8-Bit Timer/Counters 24.3.4. Events 24.3.5. Interrupts 24.3.6. Sleep Mode Operation 24.4. Register Summary - Normal Mode 24.5. Register Description - Normal Mode 24.5.1. Control A - Normal Mode 24.5.2. Control B - Normal Mode 24.5.3. Control C - Normal Mode 24.5.4. Control D - Normal Mode 24.5.5. Control Register E Clear - Normal Mode 24.5.6. Control Register E Set - Normal Mode 24.5.7. Control Register F Clear 24.5.8. Control Register F Set 24.5.9. Event Control 24.5.10. Interrupt Control Register - Normal Mode 24.5.11. Interrupt Flag Register - Normal Mode 24.5.12. Debug Control Register - Normal Mode 24.5.13. Temporary Bits for 16-Bit Access 24.5.14. Counter Register - Normal Mode 24.5.15. Period Register - Normal Mode 24.5.16. Compare n Register - Normal Mode 24.5.17. Period Buffer Register 24.5.18. Compare n Buffer Register 24.6. Register Summary - Split Mode 24.7. Register Description - Split Mode 24.7.1. Control A - Split Mode 24.7.2. Control B - Split Mode 24.7.3. Control C - Split Mode 24.7.4. Control D - Split Mode 24.7.5. Control Register E Clear - Split Mode 24.7.6. Control Register E Set - Split Mode 24.7.7. Interrupt Control Register - Split Mode 24.7.8. Interrupt Flag Register - Split Mode 24.7.9. Debug Control Register - Split Mode 24.7.10. Low Byte Timer Counter Register - Split Mode 24.7.11. High Byte Timer Counter Register - Split Mode 24.7.12. Low Byte Timer Period Register - Split Mode 24.7.13. High Byte Period Register - Split Mode 24.7.14. Compare Register n For Low Byte Timer - Split Mode 24.7.15. High Byte Compare Register n - Split Mode 25. TCB - 16-Bit Timer/Counter Type B 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.2.2. Signal Description 25.3. Functional Description 25.3.1. Definitions 25.3.2. Initialization 25.3.3. Operation 25.3.3.1. Modes 25.3.3.1.1. Periodic Interrupt Mode 25.3.3.1.2. Time-Out Check Mode 25.3.3.1.3. Input Capture on Event Mode 25.3.3.1.4. Input Capture Frequency Measurement Mode 25.3.3.1.5. Input Capture Pulse-Width Measurement Mode 25.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode 25.3.3.1.7. Single-Shot Mode 25.3.3.1.8. 8-Bit PWM Mode 25.3.3.2. Output 25.3.3.3. 32-Bit Input Capture 25.3.3.4. Noise Canceler 25.3.3.5. Synchronized with Timer/Counter Type A 25.3.4. Events 25.3.5. Interrupts 25.3.6. Sleep Mode Operation 25.4. Register Summary 25.5. Register Description 25.5.1. Control A 25.5.2. Control B 25.5.3. Event Control 25.5.4. Interrupt Control 25.5.5. Interrupt Flags 25.5.6. Status 25.5.7. Debug Control 25.5.8. Temporary Value 25.5.9. Count 25.5.10. Capture/Compare 26. RTC - Real-Time Counter 26.1. Features 26.2. Overview 26.2.1. RTC Block Diagram 26.3. Clocks 26.4. RTC Functional Description 26.4.1. Initialization 26.4.1.1. Configure the Clock CLK_RTC 26.4.1.2. Configure RTC 26.4.2. Operation - RTC 26.4.2.1. Enabling and Disabling 26.5. PIT Functional Description 26.5.1. Initialization 26.5.2. Operation - PIT 26.5.2.1. Enabling and Disabling 26.5.2.2. PIT Interrupt Timing 26.6. Crystal Error Correction 26.7. Events 26.8. Interrupts 26.9. Sleep Mode Operation 26.10. Synchronization 26.11. Debug Operation 26.12. Register Summary 26.13. Register Description 26.13.1. Control A 26.13.2. Status 26.13.3. Interrupt Control 26.13.4. Interrupt Flag 26.13.5. Temporary 26.13.6. Debug Control 26.13.7. Crystal Frequency Calibration 26.13.8. Clock Selection 26.13.9. Count 26.13.10. Period 26.13.11. Compare 26.13.12. Periodic Interrupt Timer Control A 26.13.13. Periodic Interrupt Timer Status 26.13.14. PIT Interrupt Control 26.13.15. PIT Interrupt Flag 26.13.16. Periodic Interrupt Timer Debug Control 27. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.2.2. Signal Description 27.3. Functional Description 27.3.1. Initialization 27.3.2. Operation 27.3.2.1. Frame Formats 27.3.2.2. Clock Generation 27.3.2.2.1. The Fractional Baud Rate Generator 27.3.2.3. Data Transmission 27.3.2.3.1. Disabling the Transmitter 27.3.2.4. Data Reception 27.3.2.4.1. Receiver Error Flags 27.3.2.4.2. Disabling the Receiver 27.3.2.4.3. Flushing the Receive Buffer 27.3.3. Communication Modes 27.3.3.1. Synchronous Operation 27.3.3.1.1. Clock Operation 27.3.3.1.2. External Clock Limitations 27.3.3.1.3. USART in Host SPI Mode 27.3.3.1.3.1. Frame Formats 27.3.3.1.3.2. Clock Generation 27.3.3.1.3.3. Data Transmission 27.3.3.1.3.4. Data Reception 27.3.3.1.3.5. USART in Host SPI Mode vs. SPI 27.3.3.2. Asynchronous Operation 27.3.3.2.1. Clock Recovery 27.3.3.2.2. Data Recovery 27.3.3.2.3. Error Tolerance 27.3.3.2.4. Double-Speed Operation 27.3.3.2.5. Auto-Baud 27.3.3.2.6. Half-Duplex Operation 27.3.3.2.6.1. One-Wire Mode 27.3.3.2.6.2. RS-485 Mode 27.3.3.2.7. IRCOM Mode of Operation 27.3.4. Additional Features 27.3.4.1. Parity 27.3.4.2. Start-of-Frame Detection 27.3.4.3. Multiprocessor Communication 27.3.4.3.1. Using Multiprocessor Communication 27.3.5. Events 27.3.6. Interrupts 27.4. Register Summary 27.5. Register Description 27.5.1. Receiver Data Register Low Byte 27.5.2. Receiver Data Register High Byte 27.5.3. Transmit Data Register Low Byte 27.5.4. Transmit Data Register High Byte 27.5.5. USART Status Register 27.5.6. Control A 27.5.7. Control B 27.5.8. Control C - Normal Mode 27.5.9. Control C - Host SPI Mode 27.5.10. Baud Register 27.5.11. Control D 27.5.12. Debug Control Register 27.5.13. IrDA Control Register 27.5.14. IRCOM Transmitter Pulse Length Control Register 27.5.15. IRCOM Receiver Pulse Length Control Register 28. SPI - Serial Peripheral Interface 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.2.2. Signal Description 28.3. Functional Description 28.3.1. Initialization 28.3.2. Operation 28.3.2.1. Host Mode Operation 28.3.2.1.1. Normal Mode 28.3.2.1.2. Buffer Mode 28.3.2.1.3. SS Pin Functionality in Host Mode - Multi-Host Support 28.3.2.2. Client Mode 28.3.2.2.1. Normal Mode 28.3.2.2.2. Buffer Mode 28.3.2.2.3. SS Pin Functionality in Client Mode 28.3.2.3. Data Modes 28.3.2.4. Events 28.3.2.5. Interrupts 28.4. Register Summary 28.5. Register Description 28.5.1. Control A 28.5.2. Control B 28.5.3. Interrupt Control 28.5.4. Interrupt Flags - Normal Mode 28.5.5. Interrupt Flags - Buffer Mode 28.5.6. Data 29. TWI - Two-Wire Interface 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Signal Description 29.3. Functional Description 29.3.1. General TWI Bus Concepts 29.3.2. TWI Basic Operation 29.3.2.1. Initialization 29.3.2.1.1. Host Initialization 29.3.2.1.2. Client Initialization 29.3.2.2. TWI Host Operation 29.3.2.2.1. Clock Generation 29.3.2.2.2. TWI Bus State Logic 29.3.2.2.3. Transmitting Address Packets 29.3.2.2.3.1. Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’ 29.3.2.2.3.2. Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’ 29.3.2.2.3.3. Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client 29.3.2.2.3.4. Case M4: Arbitration Lost or Bus Error 29.3.2.2.4. Transmitting Data Packets 29.3.2.2.5. Receiving Data Packets 29.3.2.3. TWI Client Operation 29.3.2.3.1. Receiving Address Packets 29.3.2.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set to ‘0’ 29.3.2.3.1.2. Case S2: Address Packet Accepted - Direction Bit Set to ‘1’ 29.3.2.3.1.3. Case S3: Stop Condition Received 29.3.2.3.1.4. Case S4: Collision 29.3.2.3.2. Receiving Data Packets 29.3.2.3.3. Transmitting Data Packets 29.3.3. Additional Features 29.3.3.1. SMBus 29.3.3.2. Multi-Host 29.3.3.3. Smart Mode 29.3.3.4. Quick Command Mode 29.3.3.5. 10-Bit Address 29.3.4. Interrupts 29.3.5. Sleep Mode Operation 29.3.6. Debug Operation 29.4. Register Summary 29.5. Register Description 29.5.1. Control A 29.5.2. Debug Control 29.5.3. Host Control A 29.5.4. Host Control B 29.5.5. Host Status 29.5.6. Host Baud Rate 29.5.7. Host Address 29.5.8. Host Data 29.5.9. Client Control A 29.5.10. Client Control B 29.5.11. Client Status 29.5.12. Client Address 29.5.13. Client Data 29.5.14. Client Address Mask 30. CRCSCAN - Cyclic Redundancy Check Memory Scan 30.1. Features 30.2. Overview 30.2.1. Block Diagram 30.3. Functional Description 30.3.1. Initialization 30.3.2. Operation 30.3.2.1. Checksum 30.3.3. Interrupts 30.3.4. Sleep Mode Operation 30.3.5. Debug Operation 30.4. Register Summary 30.5. Register Description 30.5.1. Control A 30.5.2. Control B 30.5.3. Status 31. CCL - Configurable Custom Logic 31.1. Features 31.2. Overview 31.2.1. Block Diagram 31.2.2. Signal Description 31.2.2.1. CCL Input Selection MUX 31.3. Functional Description 31.3.1. Operation 31.3.1.1. Enable-Protected Configuration 31.3.1.2. Enabling, Disabling, and Resetting 31.3.1.3. Truth Table Logic 31.3.1.4. Truth Table Inputs Selection 31.3.1.5. Filter 31.3.1.6. Edge Detector 31.3.1.7. Sequencer Logic 31.3.1.8. Clock Source Settings 31.3.2. Interrupts 31.3.3. Events 31.3.4. Sleep Mode Operation 31.4. Register Summary 31.5. Register Description 31.5.1. Control A 31.5.2. Sequencer Control 0 31.5.3. Sequencer Control 1 31.5.4. Interrupt Control 0 31.5.5. Interrupt Flag 31.5.6. LUT n Control A 31.5.7. LUT n Control B 31.5.8. LUT n Control C 31.5.9. TRUTHn 32. AC - Analog Comparator 32.1. Features 32.2. Overview 32.2.1. Block Diagram 32.2.2. Signal Description 32.3. Functional Description 32.3.1. Initialization 32.3.2. Operation 32.3.2.1. Input Hysteresis 32.3.2.2. Input Sources 32.3.2.2.1. Pin Inputs 32.3.2.2.2. Internal Inputs 32.3.2.3. Power Modes 32.3.2.4. Signal Compare and Interrupt 32.3.3. Events 32.3.4. Interrupts 32.3.5. Sleep Mode Operation 32.4. Register Summary 32.5. Register Description 32.5.1. Control A 32.5.2. MUX Control A 32.5.3. DAC Voltage Reference 32.5.4. Interrupt Control 32.5.5. Status 33. ADC - Analog-to-Digital Converter 33.1. Features 33.2. Overview 33.2.1. Block Diagram 33.2.2. Signal Description 33.3. Functional Description 33.3.1. Definitions 33.3.2. Basic Operation 33.3.3. Operation 33.3.3.1. Operation Modes 33.3.3.2. Conversion Triggers 33.3.3.3. Output Formats 33.3.3.4. ADC Clock 33.3.3.5. Input and Reference Selection 33.3.3.5.1. Programmable Gain Amplifier 33.3.3.5.2. Analog Input Circuit 33.3.3.6. Conversion Timing 33.3.3.6.1. Single Conversion 33.3.3.6.2. Series Accumulation 33.3.3.6.3. Burst Accumulation 33.3.3.6.4. Single Conversion Mode with PGA 33.3.3.6.5. Series Accumulation with PGA 33.3.3.6.6. Burst Accumulation with PGA 33.3.3.7. Temperature Measurement 33.3.3.8. Window Comparator 33.3.4. Events 33.3.5. Interrupts 33.3.6. Sleep Mode Operation 33.3.7. Debug Operation 33.4. Register Summary 33.5. Register Description 33.5.1. Control A 33.5.2. Control B 33.5.3. Control C 33.5.4. Control D 33.5.5. Interrupt Control 33.5.6. Interrupt Flags 33.5.7. Status 33.5.8. Debug Control 33.5.9. Control E 33.5.10. Control F 33.5.11. Command 33.5.12. PGA Control 33.5.13. Positive Input Multiplexer 33.5.14. Negative Input Multiplexer 33.5.15. Result 33.5.16. Sample 33.5.17. Temporary n 33.5.18. Window Comparator Low Threshold 33.5.19. Window Comparator High Threshold 34. UPDI - Unified Program and Debug Interface 34.1. Features 34.2. Overview 34.2.1. Block Diagram 34.2.2. Clocks 34.2.3. Physical Layer 34.2.4. I/O Lines and Connections 34.3. Functional Description 34.3.1. Principle of Operation 34.3.1.1. UPDI UART 34.3.1.2. BREAK Character 34.3.1.2.1. BREAK in One-Wire Mode 34.3.1.3. SYNCH Character 34.3.1.3.1. SYNCH in One-Wire Mode 34.3.2. Operation 34.3.2.1. UPDI Enabling 34.3.2.1.1. One-Wire Enable 34.3.2.1.1.1. UPDI Enable with Fuse Override of RESET Pin 34.3.2.1.1.2. UPDI Enable with High-Voltage Override of RESET Pin 34.3.2.1.1.3. Output Enable Timer Protection for GPIO Configuration 34.3.2.2. UPDI Disabling 34.3.2.2.1. Disable During Start-up 34.3.2.2.1.1. Time-Out Disable 34.3.2.2.1.2. Incorrect SYNCH pattern 34.3.2.2.2. UPDI Regular Disable 34.3.2.3. UPDI Communication Error Handling 34.3.2.4. Direction Change 34.3.3. UPDI Instruction Set 34.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 34.3.3.2. STS - Store Data to Data Space Using Direct Addressing 34.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 34.3.3.4. ST - Store Data from UPDI to Data Space Using Indirect Addressing 34.3.3.5. LDCS - Load Data from Control and Status Register Space 34.3.3.6. STCS - Store Data to Control and Status Register Space 34.3.3.7. REPEAT - Set Instruction Repeat Counter 34.3.3.8. KEY - Set Activation Key or Send System Information Block 34.3.4. CRC Checking of Flash During Boot 34.3.5. System Clock Measurement with UPDI 34.3.6. Inter-Byte Delay 34.3.7. System Information Block 34.3.8. Enabling of Key Protected Interfaces 34.3.8.1. Chip Erase 34.3.8.2. NVM Programming 34.3.8.3. User Row Programming 34.3.9. Events 34.3.10. Sleep Mode Operation 34.4. Register Summary 34.5. Register Description 34.5.1. Status A 34.5.2. Status B 34.5.3. Control A 34.5.4. Control B 34.5.5. ASI Key Status 34.5.6. ASI Reset Request 34.5.7. ASI Control A 34.5.8. ASI System Control A 34.5.9. ASI System Status 34.5.10. ASI CRC Status 35. Instruction Set Summary 36. Electrical Characteristics 36.1. Disclaimer 36.2. Absolute Maximum Ratings 36.3. General Operating Ratings 36.4. Power Considerations 36.5. Power Consumption 36.6. Wake-Up Time 36.7. Peripherals Power Consumption 36.8. BOD and POR Characteristics 36.9. External Reset Characteristics 36.10. Oscillators and Clocks 36.11. I/O Pin Characteristics 36.12. USART 36.13. SPI 36.14. TWI 36.15. VREF 36.16. ADC 36.17. TEMPSENSE 36.18. AC 36.19. UPDI 36.20. Programming Time 37. Typical Characteristics 37.1. Power Consumption 37.1.1. Active Supply Current 37.1.2. Idle Supply Current 37.1.3. Standby Supply Current 37.1.4. Power Down Supply Current 37.1.5. Power on Supply Currents 37.2. GPIO 37.2.1. GPIO Input Characteristics 37.2.2. GPIO Output Characteristics 37.2.3. GPIO Pull-Up Characteristics 37.3. VREF Characteristics 37.4. BOD Characteristics 37.4.1. BOD Current vs. VDD 37.4.2. BOD Threshold vs. Temperature 37.5. ADC Characteristics 37.5.1. Absolute Accuracy 37.5.2. DNL 37.5.3. Gain Error 37.5.4. INL 37.5.5. Offset Error 37.5.6. PGA Characteristics 37.6. TEMPSENSE Characteristics 37.7. AC Characteristics 37.8. OSC20M Characteristics 37.9. OSCULP32K Characteristics 38. Ordering Information 39. Package Drawings 39.1. Online Package Drawings 39.2. Package Marking Information 39.2.1. 14-Pin SOIC 39.2.2. 14-Pin TSSOP 39.2.3. 20-Pin SOIC 39.2.4. 20-Pin SSOP 39.2.5. 20-Pin VQFN 39.2.6. 20-Pin VQFN Wettable Flanks 39.2.7. 24-Pin VQFN 39.2.8. 24-Pin VQFN Wettable Flanks 39.3. 14-Pin SOIC 39.4. 14-Pin TSSOP 39.5. 20-Pin SOIC 39.6. 20-Pin SSOP 39.7. 20-Pin VQFN 39.8. 20-Pin VQFN Wettable Flanks 39.9. 24-Pin VQFN 39.10. 24-Pin VQFN Wettable Flanks 40. Data Sheet Revision History 40.1. Rev.B - 12/2021 40.2. Rev.A - 07/2020 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service