Core Features
- C Compiler Optimized RISC
Architecture
- Operating Speed:
- DC – 32 MHz clock
input
- 125 ns minimum
instruction time
- 16-Level Deep Hardware Stack
- Low-Current Power-on Reset
(POR)
- Configurable Power-up Timer
(PWRT)
- Brown-out Reset (BOR)
- Watchdog Timer (WDT)