| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | INDF0 | 7:0 | INDF0[7:0] | |||||||
| 0x01 | INDF1 | 7:0 | INDF1[7:0] | |||||||
| 0x02 | PCL | 7:0 | PCL[7:0] | |||||||
| 0x03 | STATUS | 7:0 | TO | PD | Z | DC | C | |||
| 0x04 | FSR0 | 7:0 | FSR0[7:0] | |||||||
| 15:8 | FSR0[15:8] | |||||||||
| 0x06 | FSR1 | 7:0 | FSR1[7:0] | |||||||
| 15:8 | FSR1[15:8] | |||||||||
| 0x08 | BSR | 7:0 | BSR[5:0] | |||||||
| 0x09 | WREG | 7:0 | WREG[7:0] | |||||||
| 0x0A | PCLATH | 7:0 | PCLATH[6:0] | |||||||
0x0B |
Reserved | |||||||||
| 0x0C | PORTA | 7:0 | RA7 | RA6 | RA5 | RA4 | RA3 | RA2 | RA1 | RA0 |
| 0x0D | PORTB | 7:0 | RB7 | RB6 | RB5 | RB4 | RB3 | RB2 | RB1 | RB0 |
| 0x0E | PORTC | 7:0 | RC7 | RC6 | RC5 | RC4 | RC3 | RC2 | RC1 | RC0 |
0x0F |
Reserved | |||||||||
| 0x10 | PORTE | 7:0 | RE3 | |||||||
0x11 |
Reserved | |||||||||
| 0x12 | TRISA | 7:0 | TRISA7 | TRISA6 | TRISA5 | TRISA4 | TRISA3 | TRISA2 | TRISA1 | TRISA0 |
| 0x13 | TRISB | 7:0 | TRISB7 | TRISB6 | TRISB5 | TRISB4 | TRISB3 | TRISB2 | TRISB1 | TRISB0 |
| 0x14 | TRISC | 7:0 | TRISC7 | TRISC6 | TRISC5 | TRISC4 | TRISC3 | TRISC2 | TRISC1 | TRISC0 |
0x15 |
Reserved | |||||||||
| 0x16 | TRISE | 7:0 | Reserved | |||||||
0x17 |
Reserved | |||||||||
| 0x18 | LATA | 7:0 | LATA7 | LATA6 | LATA5 | LATA4 | LATA3 | LATA2 | LATA1 | LATA0 |
| 0x19 | LATB | 7:0 | LATB7 | LATB6 | LATB5 | LATB4 | LATB3 | LATB2 | LATB1 | LATB0 |
| 0x1A | LATC | 7:0 | LATC7 | LATC6 | LATC5 | LATC4 | LATC3 | LATC2 | LATC1 | LATC0 |
0x1B ... 0x99 |
Reserved | |||||||||
| 0x9A | CPCON | 7:0 | CPON[1:0] | CPT | CPRDY | |||||
| 0x9B | ADRES | 7:0 | ADRES[7:0] | |||||||
| 15:8 | ADRES[15:8] | |||||||||
| 0x9D | ADCON0 | 7:0 | CHS[5:0] | GO | ON | |||||
| 0x9E | ADCON1 | 7:0 | FM | CS[2:0] | PREF[1:0] | |||||
| 0x9F | ADACT | 7:0 | ACT[3:0] | |||||||
0xA0 ... 0x010B |
Reserved | |||||||||
| 0x010C | RB1I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x010D | RB2I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x010E | RC3I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x010F | RC4I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
0x0110 ... 0x0118 |
Reserved | |||||||||
| 0x0119 | RC1REG | 7:0 | RCREG[7:0] | |||||||
| 0x011A | TX1REG | 7:0 | TXREG[7:0] | |||||||
| 0x011B | SP1BRG | 7:0 | SPBRG[7:0] | |||||||
| 15:8 | SPBRG[15:8] | |||||||||
| 0x011D | RC1STA | 7:0 | SPEN | RX9 | SREN | CREN | ADDEN | FERR | OERR | RX9D |
| 0x011E | TX1STA | 7:0 | CSRC | TX9 | TXEN | SYNC | SENDB | BRGH | TRMT | TX9D |
| 0x011F | BAUD1CON | 7:0 | ABDOVF | RCIDL | SCKP | BRG16 | WUE | ABDEN | ||
0x0120 ... 0x018B |
Reserved | |||||||||
| 0x018C | SSP1BUF | 7:0 | BUF[7:0] | |||||||
| 0x018D | SSP1ADD | 7:0 | ADD[7:0] | |||||||
| 0x018E | SSP1MSK | 7:0 | MSK[6:0] | MSK0 | ||||||
| 0x018F | SSP1STAT | 7:0 | SMP | CKE | D/A | P | S | R/W | UA | BF |
| 0x0190 | SSP1CON1 | 7:0 | WCOL | SSPOV | SSPEN | CKP | SSPM[3:0] | |||
| 0x0191 | SSP1CON2 | 7:0 | GCEN | ACKSTAT | ACKDT | ACKEN | RCEN | PEN | RSEN | SEN |
| 0x0192 | SSP1CON3 | 7:0 | ACKTIM | PCIE | SCIE | BOEN | SDAHT | SBCDE | AHEN | DHEN |
0x0193 ... 0x020B |
Reserved | |||||||||
| 0x020C | TMR1 | 7:0 | TMR1[7:0] | |||||||
| 15:8 | TMR1[15:8] | |||||||||
| 0x020E | T1CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x020F | T1GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0210 | T1GATE | 7:0 | GSS[4:0] | |||||||
| 0x0211 | T1CLK | 7:0 | CS[4:0] | |||||||
0x0212 ... 0x028B |
Reserved | |||||||||
| 0x028C | T2TMR | 7:0 | T2TMR[7:0] | |||||||
| 0x028D | T2PR | 7:0 | T2PR[7:0] | |||||||
| 0x028E | T2CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
| 0x028F | T2HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
| 0x0290 | T2CLKCON | 7:0 | CS[2:0] | |||||||
| 0x0291 | T2RST | 7:0 | RSEL[3:0] | |||||||
0x0292 ... 0x030B |
Reserved | |||||||||
| 0x030C | CCPR1 | 7:0 | CCPR[7:0] | |||||||
| 15:8 | CCPR[15:8] | |||||||||
| 0x030E | CCP1CON | 7:0 | EN | OUT | FMT | MODE[3:0] | ||||
| 0x030F | CCP1CAP | 7:0 | CTS[1:0] | |||||||
| 0x0310 | CCPR2 | 7:0 | CCPR[7:0] | |||||||
| 15:8 | CCPR[15:8] | |||||||||
| 0x0312 | CCP2CON | 7:0 | EN | OUT | FMT | MODE[3:0] | ||||
| 0x0313 | CCP2CAP | 7:0 | CTS[1:0] | |||||||
| 0x0314 | PWM3DC | 7:0 | DCL[1:0] | |||||||
| 15:8 | DCH[7:0] | |||||||||
| 0x0316 | PWM3CON | 7:0 | EN | OUT | POL | |||||
0x0317 |
Reserved | |||||||||
| 0x0318 | PWM4DC | 7:0 | DCL[1:0] | |||||||
| 15:8 | DCH[7:0] | |||||||||
| 0x031A | PWM4CON | 7:0 | EN | OUT | POL | |||||
0x031B ... 0x059B |
Reserved | |||||||||
| 0x059C | TMR0L | 7:0 | TMR0L[7:0] | |||||||
| 0x059D | TMR0H | 7:0 | TMR0H[7:0] | |||||||
| 0x059E | T0CON0 | 7:0 | EN | OUT | MD16 | OUTPS[3:0] | ||||
| 0x059F | T0CON1 | 7:0 | CS[2:0] | ASYNC | CKPS[3:0] | |||||
0x05A0 ... 0x070B |
Reserved | |||||||||
| 0x070C | PIR0 | 7:0 | TMR0IF | IOCIF | INTF | |||||
| 0x070D | PIR1 | 7:0 | CCP1IF | TMR2IF | TMR1IF | RC1IF | TX1IF | BCL1IF | SSP1IF | ADIF |
| 0x070E | PIR2 | 7:0 | CCP2IF | NVMIF | TMR1GIF | |||||
0x070F ... 0x0715 |
Reserved | |||||||||
| 0x0716 | PIE0 | 7:0 | TMR0IE | IOCIE | INTE | |||||
| 0x0717 | PIE1 | 7:0 | CCP1IE | TMR2IE | TMR1IE | RC1IE | TX1IE | BCL1IE | SSP1IE | ADIE |
| 0x0718 | PIE2 | 7:0 | CCP2IE | NVMIE | TMR1GIE | |||||
0x0719 ... 0x080B |
Reserved | |||||||||
| 0x080C | WDTCON | 7:0 | CS | PS[4:0] | SEN | |||||
0x080D ... 0x0810 |
Reserved | |||||||||
| 0x0811 | BORCON | 7:0 | SBOREN | BORRDY | ||||||
0x0812 |
Reserved | |||||||||
| 0x0813 | PCON0 | 7:0 | STKOVF | STKUNF | RWDT | RMCLR | RI | POR | BOR | |
| 0x0814 | PCON1 | 7:0 | MEMV | |||||||
0x0815 ... 0x088D |
Reserved | |||||||||
| 0x088E | OSCCON | 7:0 | COSC[1:0] | |||||||
0x088F |
Reserved | |||||||||
| 0x0890 | OSCSTAT | 7:0 | HFOR | MFOR | LFOR | ADOR | SFOR | |||
| 0x0891 | OSCEN | 7:0 | HFOEN | MFOEN | LFOEN | ADOEN | ||||
| 0x0892 | OSCTUNE | 7:0 | TUN[5:0] | |||||||
| 0x0893 | OSCFRQ | 7:0 | FRQ[2:0] | |||||||
0x0894 ... 0x090B |
Reserved | |||||||||
| 0x090C | FVRCON | 7:0 | FVREN | FVRRDY | ADFVR[1:0] | |||||
0x090D ... 0x1C8B |
Reserved | |||||||||
| 0x1C8C | NVMADR | 7:0 | NVMADR[7:0] | |||||||
| 15:8 | NVMADR[14:8] | |||||||||
| 0x1C8E | NVMDAT | 7:0 | NVMDAT[7:0] | |||||||
| 15:8 | NVMDAT[13:8] | |||||||||
| 0x1C90 | NVMCON1 | 7:0 | NVMREGS | LWLO | FREE | WRERR | WREN | WR | RD | |
| 0x1C91 | NVMCON2 | 7:0 | NVMCON2[7:0] | |||||||
0x1C92 ... 0x1E8E |
Reserved | |||||||||
| 0x1E8F | PPSLOCK | 7:0 | PPSLOCKED | |||||||
| 0x1E90 | INTPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E91 | T0CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E92 | T1CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E93 | T1GPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E94 ... 0x1E9B |
Reserved | |||||||||
| 0x1E9C | T2INPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E9D ... 0x1EA0 |
Reserved | |||||||||
| 0x1EA1 | CCP1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1EA2 | CCP2PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1EA3 ... 0x1EC2 |
Reserved | |||||||||
| 0x1EC3 | ADACTPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1EC4 |
Reserved | |||||||||
| 0x1EC5 | SSP1CLKPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1EC6 | SSP1DATPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1EC7 | SSP1SSPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1EC8 ... 0x1ECA |
Reserved | |||||||||
| 0x1ECB | RX1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1ECC | CK1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1ECD ... 0x1F0F |
Reserved | |||||||||
| 0x1F10 | RA0PPS | 7:0 | RA0PPS[5:0] | |||||||
| 0x1F11 | RA1PPS | 7:0 | RA1PPS[5:0] | |||||||
| 0x1F12 | RA2PPS | 7:0 | RA2PPS[5:0] | |||||||
| 0x1F13 | RA3PPS | 7:0 | RA3PPS[5:0] | |||||||
| 0x1F14 | RA4PPS | 7:0 | RA4PPS[5:0] | |||||||
| 0x1F15 | RA5PPS | 7:0 | RA5PPS[5:0] | |||||||
| 0x1F16 | RA6PPS | 7:0 | RA6PPS[5:0] | |||||||
| 0x1F17 | RA7PPS | 7:0 | RA7PPS[5:0] | |||||||
| 0x1F18 | RB0PPS | 7:0 | RB0PPS[5:0] | |||||||
| 0x1F19 | RB1PPS | 7:0 | RB1PPS[5:0] | |||||||
| 0x1F1A | RB2PPS | 7:0 | RB2PPS[5:0] | |||||||
| 0x1F1B | RB3PPS | 7:0 | RB3PPS[5:0] | |||||||
| 0x1F1C | RB4PPS | 7:0 | RB4PPS[5:0] | |||||||
| 0x1F1D | RB5PPS | 7:0 | RB5PPS[5:0] | |||||||
| 0x1F1E | RB6PPS | 7:0 | RB6PPS[5:0] | |||||||
| 0x1F1F | RB7PPS | 7:0 | RB7PPS[5:0] | |||||||
| 0x1F20 | RC0PPS | 7:0 | RC0PPS[5:0] | |||||||
| 0x1F21 | RC1PPS | 7:0 | RC1PPS[5:0] | |||||||
| 0x1F22 | RC2PPS | 7:0 | RC2PPS[5:0] | |||||||
| 0x1F23 | RC3PPS | 7:0 | RC3PPS[5:0] | |||||||
| 0x1F24 | RC4PPS | 7:0 | RC4PPS[5:0] | |||||||
| 0x1F25 | RC5PPS | 7:0 | RC5PPS[5:0] | |||||||
| 0x1F26 | RC6PPS | 7:0 | RC6PPS[5:0] | |||||||
| 0x1F27 | RC7PPS | 7:0 | RC7PPS[5:0] | |||||||
0x1F28 ... 0x1F37 |
Reserved | |||||||||
| 0x1F38 | ANSELA | 7:0 | ANSELA7 | ANSELA6 | ANSELA5 | ANSELA4 | ANSELA3 | ANSELA2 | ANSELA1 | ANSELA0 |
| 0x1F39 | WPUA | 7:0 | WPUA7 | WPUA6 | WPUA5 | WPUA4 | WPUA3 | WPUA2 | WPUA1 | WPUA0 |
| 0x1F3A | ODCONA | 7:0 | ODCA7 | ODCA6 | ODCA5 | ODCA4 | ODCA3 | ODCA2 | ODCA1 | ODCA0 |
| 0x1F3B | SLRCONA | 7:0 | SLRA7 | SLRA6 | SLRA5 | SLRA4 | SLRA3 | SLRA2 | SLRA1 | SLRA0 |
| 0x1F3C | INLVLA | 7:0 | INLVLA7 | INLVLA6 | INLVLA5 | INLVLA4 | INLVLA3 | INLVLA2 | INLVLA1 | INLVLA0 |
| 0x1F3D | IOCAP | 7:0 | IOCAP7 | IOCAP6 | IOCAP5 | IOCAP4 | IOCAP3 | IOCAP2 | IOCAP1 | IOCAP0 |
| 0x1F3E | IOCAN | 7:0 | IOCAN7 | IOCAN6 | IOCAN5 | IOCAN4 | IOCAN3 | IOCAN2 | IOCAN1 | IOCAN0 |
| 0x1F3F | IOCAF | 7:0 | IOCAF7 | IOCAF6 | IOCAF5 | IOCAF4 | IOCAF3 | IOCAF2 | IOCAF1 | IOCAF0 |
0x1F40 ... 0x1F42 |
Reserved | |||||||||
| 0x1F43 | ANSELB | 7:0 | ANSELB7 | ANSELB6 | ANSELB5 | ANSELB4 | ANSELB3 | ANSELB2 | ANSELB1 | ANSELB0 |
| 0x1F44 | WPUB | 7:0 | WPUB7 | WPUB6 | WPUB5 | WPUB4 | WPUB3 | WPUB2 | WPUB1 | WPUB0 |
| 0x1F45 | ODCONB | 7:0 | ODCB7 | ODCB6 | ODCB5 | ODCB4 | ODCB3 | ODCB2 | ODCB1 | ODCB0 |
| 0x1F46 | SLRCONB | 7:0 | SLRB7 | SLRB6 | SLRB5 | SLRB4 | SLRB3 | SLRB2 | SLRB1 | SLRB0 |
| 0x1F47 | INLVLB | 7:0 | INLVLB7 | INLVLB6 | INLVLB5 | INLVLB4 | INLVLB3 | INLVLB2 | INLVLB1 | INLVLB0 |
| 0x1F48 | IOCBP | 7:0 | IOCBP7 | IOCBP6 | IOCBP5 | IOCBP4 | IOCBP3 | IOCBP2 | IOCBP1 | IOCBP0 |
| 0x1F49 | IOCBN | 7:0 | IOCBN7 | IOCBN6 | IOCBN5 | IOCBN4 | IOCBN3 | IOCBN2 | IOCBN1 | IOCBN0 |
| 0x1F4A | IOCBF | 7:0 | IOCBF7 | IOCBF6 | IOCBF5 | IOCBF4 | IOCBF3 | IOCBF2 | IOCBF1 | IOCBF0 |
0x1F4B ... 0x1F4D |
Reserved | |||||||||
| 0x1F4E | ANSELC | 7:0 | ANSELC7 | ANSELC6 | ANSELC5 | ANSELC4 | ANSELC3 | ANSELC2 | ANSELC1 | ANSELC0 |
| 0x1F4F | WPUC | 7:0 | WPUC7 | WPUC6 | WPUC5 | WPUC4 | WPUC3 | WPUC2 | WPUC1 | WPUC0 |
| 0x1F50 | ODCONC | 7:0 | ODCC7 | ODCC6 | ODCC5 | ODCC4 | ODCC3 | ODCC2 | ODCC1 | ODCC0 |
| 0x1F51 | SLRCONC | 7:0 | SLRC7 | SLRC6 | SLRC5 | SLRC4 | SLRC3 | SLRC2 | SLRC1 | SLRC0 |
| 0x1F52 | INLVLC | 7:0 | INLVLC7 | INLVLC6 | INLVLC5 | INLVLC4 | INLVLC3 | INLVLC2 | INLVLC1 | INLVLC0 |
| 0x1F53 | IOCCP | 7:0 | IOCCP7 | IOCCP6 | IOCCP5 | IOCCP4 | IOCCP3 | IOCCP2 | IOCCP1 | IOCCP0 |
| 0x1F54 | IOCCN | 7:0 | IOCCN7 | IOCCN6 | IOCCN5 | IOCCN4 | IOCCN3 | IOCCN2 | IOCCN1 | IOCCN0 |
| 0x1F55 | IOCCF | 7:0 | IOCCF7 | IOCCF6 | IOCCF5 | IOCCF4 | IOCCF3 | IOCCF2 | IOCCF1 | IOCCF0 |
0x1F56 ... 0x1F64 |
Reserved | |||||||||
| 0x1F65 | WPUE | 7:0 | WPUE3 | |||||||
0x1F66 ... 0x1F67 |
Reserved | |||||||||
| 0x1F68 | INLVLE | 7:0 | INLVLE3 | |||||||
| 0x1F69 | IOCEP | 7:0 | IOCEP3 | |||||||
| 0x1F6A | IOCEN | 7:0 | IOCEN3 | |||||||
| 0x1F6B | IOCEF | 7:0 | IOCEF3 | |||||||
0x1F6C ... 0x8004 |
Reserved | |||||||||
| 0x8005 | REVISIONID | 7:0 | MJRREV[1:0] | MNRREV[5:0] | ||||||
| 15:8 | Reserved | Reserved | MJRREV[5:2] | |||||||
| 0x8006 | DEVICEID | 7:0 | DEV[7:0] | |||||||
| 15:8 | Reserved | Reserved | DEV[11:8] | |||||||
| 0x8007 | CONFIG1 | 7:0 | RSTOSC[1:0] | FEXTOSC[1:0] | ||||||
| 15:8 | VDDAR | CLKOUTEN | ||||||||
| 0x8008 | CONFIG2 | 7:0 | BOREN[1:0] | WDTE[1:0] | PWRTS[1:0] | MCLRE | ||||
| 15:8 | DEBUG | STVREN | PPS1WAY | BORV | ||||||
| 0x8009 | CONFIG3 | 7:0 | ||||||||
| 15:8 | ||||||||||
| 0x800A | CONFIG4 | 7:0 | WRTAPP | SAFEN | BBEN | BBSIZE[2:0] | ||||
| 15:8 | LVP | WRTSAF | WRTC | WRTB | ||||||
| 0x800B | CONFIG5 | 7:0 | CP | |||||||
| 15:8 | ||||||||||