SSPxCON2

Control Register for I2C Operation Only

Notes:
  1. 1.The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
  2. 2.If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
Name:
SSPxCON2
Offset:
0x0191
Reset:
Access:
Bit76543210
GCENACKSTATACKDTACKENRCENPENRSENSEN
AccessR/WR/W/HCR/WR/WR/WR/WR/WR/W
Reset00000000

Bit 7 – GCEN

General Call Enable bit (Client mode only)
ValueNameDescription
x Host mode Don’t care
1 Client mode General Call is enabled
0 Client mode General Call is not enabled

Bit 6 – ACKSTAT: Acknowledge Status bit (Host Transmit mode only)

Acknowledge Status bit (Host Transmit mode only)

ValueDescription
1 Acknowledge was not received from client
0 Acknowledge was received from client

Bit 5 – ACKDT

Acknowledge Data bit (Host Receive mode only)(1)
ValueDescription
1 Not Acknowledge
0 Acknowledge

Bit 4 – ACKEN

Acknowledge Sequence Enable bit(2)
ValueDescription
1 Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; 
automatically cleared by hardware
0 Acknowledge sequence is Idle

Bit 3 – RCEN

Receive Enable bit (Host Receive mode only)(2)
ValueDescription
1

Enables Receive mode for I2C
0

Receive is Idle

Bit 2 – PEN

Stop Condition Enable bit (Host mode only)(2)
ValueDescription
1 Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 Stop condition is Idle

Bit 1 – RSEN

Repeated Start Condition Enable bit (Host mode only)(2)
ValueDescription
1 Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 Repeated Start condition is Idle

Bit 0 – SEN

Start Condition Enable bit(2)
ValueNameDescription
1 Host Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 Host Start condition is Idle
1 Client Clock stretching is enabled
0 Client Clock stretching is disabled