Conversion Clock

The conversion clock source is selected via the ADC Conversion Clock Select (CS) bits. The available clock sources include several derivatives of the system clock (FOSC), as well as a dedicated internal fixed-frequency clock referred to as the ADCRC.

The time to complete one bit conversion is defined as the TAD. Refer to Figure 1 for complete timing details of the ADC conversion.

For a correct conversion, the appropriate TAD specification must be met. Refer to the ADC Timing Specifications table in the “Electrical Specifications” section for more details. Table 1 gives examples of appropriate ADC clock selections.

Important:
Table 1. ADC Clock Period (TAD) for Different Device Frequencies (FOSC)
ADC Clock Source CS[2:0] ADC Clock Period (TAD) for Different Device Frequencies (FOSC)
32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 ‘b000 62.5 ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns 2.0 µs
FOSC/4 ‘b100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns 1.0 µs 4.0 µs
FOSC/8 ‘b001 250 ns(2) 400 ns(2) 500 ns 1.0 µs 2.0 µs 8.0 µs
FOSC/16 ‘b101 500 ns 800 ns 1.0 µs 2.0 µs 4.0 µs 16.0 µs(2)
FOSC/32 ‘b010 1.0 µs 1.6 µs 2.0 µs 4.0 µs 8.0 µs 32.0 µs(2)
FOSC/64 ‘b110 2.0 µs 3.2 µs 4.0 µs 8.0 µs 16.0 µs(2) 64.0 µs(2)
ADCRC ‘bx11 1.0 - 6.0(1,3)
Notes:
  1. 1.Refer to the “Electrical Specifications” section to see the TAD parameter for the ADCRC source typical TAD value.
  2. 2.These values violate the required TAD time.
  3. 3.The ADC clock period (TAD) and the total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be performed with the device in Sleep mode.
Figure 1. 10-Bit Analog-to-Digital Conversion TAD Cycles