CONFIG2

Configuration Word 2
Notes:
  1. 1.The DEBUG bit is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit needs to be maintained as a ‘1’.
  2. 2.The higher voltage selection is recommended for operation at or above 16 MHz.
  3. 3.When enabled, Brown-out Reset voltage (VBOR) is set by the BORV bit.
Name:
CONFIG2
Offset:
0x8008
Reset:
Access:
Bit15141312111098
DEBUGSTVRENPPS1WAYBORV
AccessR/WR/WR/WR/W
Reset1111
Bit76543210
BOREN[1:0]WDTE[1:0]PWRTS[1:0]MCLRE
AccessR/WR/WR/WR/WR/WR/WR/W
Reset1111111

Bit 13 – DEBUG: Debugger Enable(1)

Debugger Enable(1)

ValueDescription
1 Background debugger disabled
0 Background debugger enabled

Bit 12 – STVREN: Stack Overflow/Underflow Reset Enable

Stack Overflow/Underflow Reset Enable

ValueDescription
1 Stack Overflow or Underflow will cause a Reset
0 Stack Overflow or Underflow will not cause a Reset

Bit 11 – PPS1WAY: PPSLOCKED One-Way Set Enable

PPSLOCKED One-Way Set Enable

ValueDescription
1 The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCKED is set, all future changes to PPS registers are prevented
0 The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required)

Bit 9 – BORV: Brown-out Reset (BOR) Voltage Selection(2)

Brown-out Reset (BOR) Voltage Selection(2)

ValueDescription
1 Brown-out Reset voltage (VBOR) set to 1.9V
0 Brown-out Reset voltage (VBOR) set to 2.85V

Bits 7:6 – BOREN[1:0]: Brown-out Reset (BOR) Enable(3)

Brown-out Reset (BOR) Enable(3)

ValueDescription
11 Brown-out Reset enabled, the SBOREN bit is ignored
10 Brown-out Reset enabled while running, disabled in Sleep; the SBOREN bit is ignored
01 Brown-out Reset enabled according to SBOREN
00 Brown-out Reset disabled

Bits 4:3 – WDTE[1:0]: Watchdog Timer (WDT) Enable

Watchdog Timer (WDT) Enable

ValueDescription
11 WDT enabled regardless of Sleep; the SEN bit of WDTCON is ignored
10 WDT enabled while Sleep = 0, suspended when Sleep = 1; the SEN bit of WDTCON is ignored
01 WDT enabled/disabled by the SEN bit of WDTCON
00 WDT disabled, the SEN bit of WDTCON is ignored

Bits 2:1 – PWRTS[1:0]: Power-Up Timer (PWRT) Selection

Power-Up Timer (PWRT) Selection

ValueDescription
11 PWRT disabled
10 PWRT is set at 64 ms
01 PWRT is set at 16 ms
00 PWRT is set at 1 ms

Bit 0 – MCLRE: Master Clear (MCLR) Enable

Master Clear (MCLR) Enable

ValueNameDescription
x If LVP = 1 MCLR pin is MCLR
1 If LVP = 0 MCLR pin is MCLR
0 If LVP = 0 MCLR pin function is port-defined function