Contents

Introduction PIC16F152 Family Types Core Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Block Diagram 4. Packages 5. Pin Diagrams 6. Pin Allocation Tables 7. Guidelines for Getting Started with PIC16F152 Microcontrollers 7.1. Basic Connection Requirements 7.2. Power Supply Pins 7.2.1. Decoupling Capacitors 7.2.2. Tank Capacitors 7.3. Master Clear (MCLR) Pin 7.4. In-Circuit Serial Programming (ICSP) Pins 7.5. Unused I/Os 8. Register and Bit Naming Conventions 8.1. Register Names 8.2. Bit Names 8.2.1. Short Bit Names 8.2.2. Long Bit Names 8.2.3. Bit Fields 8.3. Register and Bit Naming Exceptions 8.3.1. Status, Interrupt and Mirror Bits 9. Register Legend 10. Enhanced Mid-Range CPU 10.1. Automatic Interrupt Context Saving 10.2. 16-Level Stack with Overflow and Underflow 10.3. File Select Registers 10.4. Instruction Set 11. Device Configuration 11.1. Configuration Words 11.2. Code Protection 11.3. Write Protection 11.4. User ID 11.5. Device ID and Revision ID 11.6. Register Definitions: Configuration Settings 11.6.1. CONFIG1 11.6.2. CONFIG2 11.6.3. CONFIG3 11.6.4. CONFIG4 11.6.5. CONFIG5 11.7. Register Definitions: Device ID and Revision ID 11.7.1. Device ID 11.7.2. Revision ID 12. Memory Organization 12.1. Program Memory Organization 12.1.1. Reading Program Memory as Data 12.1.1.1. RETLW Instruction 12.1.1.2. Indirect Read with FSR 12.1.2. Memory Access Partition (MAP) 12.1.2.1. Application Block 12.1.2.2. Boot Block 12.1.2.3. Storage Area Flash 12.1.2.4. Memory Write Protection 12.1.2.5. Memory Violation 12.1.3. Device Information Area (DIA) 12.1.3.1. Microchip Unique Identifier (MUI) 12.1.3.2. External Unique Identifier (EUI) 12.1.3.3. Fixed Voltage Reference (FVR) Data 12.1.4. Device Configuration Information (DCI) 12.1.4.1. DIA and DCI Access 12.2. Data Memory Organization 12.2.1. Bank Selection 12.2.2. Core Registers 12.2.3. Special Function Register 12.2.4. General Purpose RAM 12.2.5. Common RAM 12.2.6. Device Memory Maps 12.3. STATUS Register 12.4. PCL and PCLATH 12.4.1. Modifying PCL 12.4.2. Computed GOTO 12.4.3. Computed Function Calls 12.4.4. Branching 12.5. Stack 12.5.1. Accessing the Stack 12.5.2. Overflow/Underflow Reset 12.6. Indirect Addressing 12.6.1. Traditional/Banked Data Memory 12.6.2. Linear Data Memory 12.6.3. Program Flash Memory 12.7. Register Definitions: Memory Organization 12.7.1. INDF0 12.7.2. INDF1 12.7.3. PCL 12.7.4. STATUS 12.7.5. FSR0 12.7.6. FSR1 12.7.7. BSR 12.7.8. WREG 12.7.9. PCLATH 12.8. Register Summary - Memory Organization 13. Resets 13.1. Power-on Reset (POR) 13.1.1. Programming Mode Exit 13.2. Brown-out Reset (BOR) 13.2.1. BOR Is Always On 13.2.2. BOR Is Off in Sleep 13.2.3. BOR Controlled by Software 13.2.4. BOR Is Always Off 13.3. MCLR Reset 13.3.1. MCLR Enabled 13.3.2. MCLR Disabled 13.4. Watchdog Timer (WDT) Reset 13.5. RESET Instruction 13.6. Stack Overflow/Underflow Reset 13.7. Power-Up Timer (PWRT) 13.8. Start-Up Sequence 13.9. Memory Execution Violation 13.10. Determining the Cause of a Reset 13.11. Power Control (PCONx) Register 13.12. Register Definitions: Power Control 13.12.1. BORCON 13.12.2. PCON0 13.12.3. PCON1 13.13. Register Summary - Power Control 14. OSC - Oscillator Module 14.1. Oscillator Module Overview 14.2. Clock Source Types 14.2.1. External Clock Sources 14.2.1.1. EC Mode 14.2.2. Internal Clock Sources 14.2.2.1. HFINTOSC 14.2.2.1.1. HFINTOSC Frequency Tuning 14.2.2.2. MFINTOSC 14.2.2.3. SFINTOSC 14.2.2.4. LFINTOSC 14.2.2.5. ADCRC 14.2.3. Oscillator Status and Manual Enable 14.3. Register Definitions: Oscillator Control 14.3.1. OSCCON 14.3.2. OSCSTAT 14.3.3. OSCEN 14.3.4. OSCFRQ 14.3.5. OSCTUNE 14.4. Register Summary - Oscillator Control 15. Interrupts 15.1. INTCON Register 15.2. PIE Registers 15.3. PIR Registers 15.4. Operation 15.5. Interrupt Latency 15.6. Interrupts During Sleep 15.7. INT Pin 15.8. Automatic Context Saving 15.9. Register Definitions: Interrupt Control 15.9.1. INTCON 15.9.2. PIE0 15.9.3. PIE1 15.9.4. PIE2 15.9.5. PIR0 15.9.6. PIR1 15.9.7. PIR2 15.10. Register Summary - Interrupt Control 16. Sleep Mode 16.1. Sleep Mode Operation 16.1.1. Wake-Up from Sleep 16.1.2. Wake-Up Using Interrupts 17. WDT - Watchdog Timer 17.1. Selectable Clock Sources 17.2. WDT Operating Modes 17.2.1. WDT Is Always On 17.2.2. WDT Is Off During Sleep 17.2.3. WDT Controlled by Software 17.2.4. WDT Is Off 17.3. WDT Time-Out Period 17.4. Clearing the WDT 17.5. WDT Operation During Sleep 17.6. Register Definitions: WDT Control 17.6.1. WDTCON 17.7. Register Summary - WDT Control 18. NVM - Nonvolatile Memory Control 18.1. Program Flash Memory (PFM) 18.1.1. FSR and INDF Access 18.1.1.1. FSR Read 18.1.1.2. FSR Write 18.1.2. NVMREG Access 18.1.2.1. NVMREG Read Operation 18.1.2.2. NVM Unlock Sequence 18.1.2.3. NVMREG Erase of Program Memory 18.1.2.4. NVMREG Write to Program Memory 18.1.2.5. Modifying Flash Program Memory 18.1.2.6. NVMREG Access to DIA, DCI, User ID, Device ID, Revision ID, and Configuration Words 18.1.2.7. Write Verify 18.1.2.8. WRERR Bit 18.2. Register Definitions: Nonvolatile Memory Control 18.2.1. NVMADR 18.2.2. NVMDAT 18.2.3. NVMCON1 18.2.4. NVMCON2 18.3. Register Summary - NVM Control 19. I/O Ports 19.1. Overview 19.2. PORTx - Data Register 19.3. LATx - Output Latch 19.4. TRISx - Direction Control 19.5. ANSELx - Analog Control 19.6. WPUx - Weak Pull-Up Control 19.7. INLVLx - Input Threshold Control 19.8. SLRCONx - Slew Rate Control 19.9. ODCONx - Open-Drain Control 19.10. Edge Selectable Interrupt-on-Change 19.11. I2C Pad Control 19.12. I/O Priorities 19.13. MCLR/VPP/RE3 Pin 19.14. Register Definitions: Port Control 19.14.1. PORTx 19.14.2. LATx 19.14.3. TRISx 19.14.4. ANSELx 19.14.5. WPUx 19.14.6. INLVLx 19.14.7. SLRCONx 19.14.8. ODCONx 19.14.9. RxyI2C 19.15. Register Summary - IO Ports 20. IOC - Interrupt-on-Change 20.1. Overview 20.2. Enabling the Module 20.3. Individual Pin Configuration 20.4. Interrupt Flags 20.5. Clearing Interrupt Flags 20.6. Operation in Sleep 20.7. Register Definitions: Interrupt-on-Change Control 20.7.1. IOCxF 20.7.2. IOCxN 20.7.3. IOCxP 20.8. Register Summary - Interrupt-on-Change 21. PPS - Peripheral Pin Select Module 21.1. Overview 21.2. PPS Inputs 21.3. PPS Outputs 21.4. Bidirectional Pins 21.5. PPS Lock 21.5.1. PPS One-Way Lock 21.6. Operation During Sleep 21.7. Effects of a Reset 21.8. Register Definitions: Peripheral Pin Select (PPS) 21.8.1. xxxPPS 21.8.2. RxyPPS 21.8.3. PPSLOCK 21.9. Register Summary - Peripheral Pin Select Module 22. TMR0 - Timer0 Module 22.1. Timer0 Operation 22.1.1. 8-Bit Mode 22.1.2. 16-Bit Mode 22.2. Clock Selection 22.2.1. Synchronous Mode 22.2.2. Asynchronous Mode 22.2.3. Programmable Prescaler 22.2.4. Programmable Postscaler 22.3. Timer0 Output and Interrupt 22.3.1. Timer0 Output 22.3.2. Timer0 Interrupt 22.3.3. Timer0 Example 22.4. Operation During Sleep 22.5. Register Definitions: Timer0 Control 22.5.1. T0CON0 22.5.2. T0CON1 22.5.3. TMR0H 22.5.4. TMR0L 22.6. Register Summary - Timer0 23. TMR1 - Timer1 Module with Gate Control 23.1. Timer1 Operation 23.2. Clock Source Selection 23.2.1. Internal Clock Source 23.2.2. External Clock Source 23.3. Timer1 Prescaler 23.4. Timer1 Operation in Asynchronous Counter Mode 23.4.1. Reading and Writing TMRx in Asynchronous Counter Mode 23.5. Timer1 16-Bit Read/Write Mode 23.6. Timer1 Gate 23.6.1. Timer1 Gate Enable 23.6.2. Timer1 Gate Source Selection 23.6.3. Timer1 Gate Toggle Mode 23.6.4. Timer1 Gate Single Pulse Mode 23.6.5. Timer1 Gate Value Status 23.6.6. Timer1 Gate Event Interrupt 23.7. Timer1 Interrupt 23.8. Timer1 Operation During Sleep 23.9. CCP Capture/Compare Time Base 23.10. CCP Special Event Trigger 23.11. Register Definitions: Timer1 Control 23.11.1. TxCON 23.11.2. TxGCON 23.11.3. TxCLK 23.11.4. TxGATE 23.11.5. TMRx 23.12. Register Summary - Timer1 24. TMR2 - Timer2 Module 24.1. Timer2 Operation 24.1.1. Free-Running Period Mode 24.1.2. One Shot Mode 24.1.3. Monostable Mode 24.2. Timer2 Output 24.3. External Reset Sources 24.4. Timer2 Interrupt 24.5. PSYNC Bit 24.6. CSYNC Bit 24.7. Operating Modes 24.8. Operation Examples 24.8.1. Software Gate Mode 24.8.2. Hardware Gate Mode 24.8.3. Edge Triggered Hardware Limit Mode 24.8.4. Level Triggered Hardware Limit Mode 24.8.5. Software Start One Shot Mode 24.8.6. Edge Triggered One Shot Mode 24.8.7. Edge Triggered Hardware Limit One Shot Mode 24.8.8. Level Reset, Edge Triggered Hardware Limit One Shot Modes 24.8.9. Edge Triggered Monostable Modes 24.8.10. Level Triggered Hardware Limit One Shot Modes 24.9. Timer2 Operation During Sleep 24.10. Register Definitions: Timer2 Control 24.10.1. TxTMR 24.10.2. TxPR 24.10.3. TxCON 24.10.4. TxHLT 24.10.5. TxCLKCON 24.10.6. TxRST 24.11. Register Summary - Timer2 25. CCP - Capture/Compare/PWM Module 25.1. CCP Module Configuration 25.1.1. CCP Modules and Timer Resources 25.1.2. Open-Drain Output Option 25.2. Capture Mode 25.2.1. Capture Sources 25.2.2. Timer1 Mode for Capture 25.2.3. Software Interrupt Mode 25.2.4. CCP Prescaler 25.2.5. Capture During Sleep 25.3. Compare Mode 25.3.1. CCPx Pin Configuration 25.3.2. Timer1 Mode for Compare 25.3.3. Compare During Sleep 25.4. PWM Overview 25.4.1. Standard PWM Operation 25.4.2. Timer2 Timer Resource 25.4.3. PWM Period 25.4.4. PWM Duty Cycle 25.4.5. PWM Resolution 25.4.6. Operation in Sleep Mode 25.4.7. Changes in System Clock Frequency 25.4.8. Effects of Reset 25.4.9. Setup for PWM Operation 25.5. Register Definitions: CCP Control 25.5.1. CCPxCON 25.5.2. CCPxCAP 25.5.3. CCPRx 25.6. Register Summary - CCP Control 26. PWM - Pulse-Width Modulation 26.1. Fundamental Operation 26.2. PWM Output Polarity 26.3. PWM Period 26.4. PWM Duty Cycle 26.5. PWM Resolution 26.6. Operation in Sleep Mode 26.7. Changes in System Clock Frequency 26.8. Effects of Reset 26.9. Setup for PWM Operation Using PWMx Output Pins 26.9.1. PWMx Pin Configuration 26.10. Setup for PWM Operation to Other Device Peripherals 26.11. Register Definitions: PWM Control 26.11.1. PWMxCON 26.11.2. PWMxDC 26.12. Register Summary - PWM 27. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter 27.1. EUSART Asynchronous Mode 27.1.1. EUSART Asynchronous Transmitter 27.1.1.1. Enabling the Transmitter 27.1.1.2. Transmitting Data 27.1.1.3. Transmit Data Polarity 27.1.1.4. Transmit Interrupt Flag 27.1.1.5. TSR Status 27.1.1.6. Transmitting 9-Bit Characters 27.1.1.7. Asynchronous Transmission Setup 27.1.2. EUSART Asynchronous Receiver 27.1.2.1. Enabling the Receiver 27.1.2.2. Receiving Data 27.1.2.3. Receive Interrupts 27.1.2.4. Receive Framing Error 27.1.2.5. Receive Overrun Error 27.1.2.6. Receiving 9-Bit Characters 27.1.2.7. Address Detection 27.1.2.8. Asynchronous Reception Setup 27.1.2.9. 9-Bit Address Detection Mode Setup 27.2. Clock Accuracy with Asynchronous Operation 27.3. EUSART Baud Rate Generator (BRG) 27.3.1. Auto-Baud Detect 27.3.2. Auto-Baud Overflow 27.3.3. Auto-Wake-Up on Break 27.3.3.1. Special Considerations 27.3.4. Break Character Sequence 27.3.4.1. Break and Sync Transmit Sequence 27.3.5. Receiving a Break Character 27.4. EUSART Synchronous Mode 27.4.1. Synchronous Host Mode 27.4.1.1. Host Clock 27.4.1.2. Clock Polarity 27.4.1.3. Synchronous Host Transmission 27.4.1.4. Synchronous Host Transmission Setup 27.4.1.5. Synchronous Host Reception 27.4.1.6. Client Clock 27.4.1.7. Receive Overrun Error 27.4.1.8. Receiving 9-Bit Characters 27.4.1.9. Synchronous Host Reception Setup 27.4.2. Synchronous Client Mode 27.4.2.1. EUSART Synchronous Client Transmit 27.4.2.2. Synchronous Client Transmission Setup 27.4.2.3. EUSART Synchronous Client Reception 27.4.2.4. Synchronous Client Reception Setup 27.5. EUSART Operation During Sleep 27.5.1. Synchronous Receive During Sleep 27.5.2. Synchronous Transmit During Sleep 27.6. Register Definitions: EUSART Control 27.6.1. TXxSTA 27.6.2. RCxSTA 27.6.3. BAUDxCON 27.6.4. RCxREG 27.6.5. TXxREG 27.6.6. SPxBRG 27.7. Register Summary - EUSART 28. MSSP - Host Synchronous Serial Port Module 28.1. SPI Mode Overview 28.1.1. SPI Mode Registers 28.1.2. SPI Mode Operation 28.1.2.1. SPI Host Mode 28.1.2.2. SPI Client Mode 28.1.2.3. Daisy-Chain Configuration 28.1.2.4. Client Select Synchronization 28.1.2.5. SPI Operation in Sleep Mode 28.2. I2C Mode Overview 28.2.1. I2C Mode Registers 28.2.2. I2C Mode Operation 28.2.2.1. Definition of I2C Terminology 28.2.2.2. Byte Format 28.2.2.3. SDA and SCL Pins 28.2.2.4. SDA Hold Time 28.2.2.5. Clock Stretching 28.2.2.6. Arbitration 28.2.2.7. Start Condition 28.2.2.8. Stop Condition 28.2.2.9. Start/Stop Condition Interrupt Masking 28.2.2.10. Restart Condition 28.2.2.11. Acknowledge Sequence 28.2.3. I2C Client Mode Operation 28.2.3.1. Client Mode Addresses 28.2.3.1.1. I2C Client 7-Bit Addressing Mode 28.2.3.1.2. I2C Client 10-Bit Addressing Mode 28.2.3.2. Clock Stretching 28.2.3.2.1. Normal Clock Stretching 28.2.3.2.2. 10-Bit Addressing Mode 28.2.3.2.3. Byte NACKing 28.2.3.3. Clock Synchronization and the CKP Bit 28.2.3.4. General Call Address Support 28.2.3.5. SSP Mask Register 28.2.3.6. Client Reception 28.2.3.6.1. 7-Bit Addressing Reception 28.2.3.6.2. 7-Bit Reception with AHEN and DHEN 28.2.3.6.3. Client Mode 10-Bit Address Reception 28.2.3.6.4. 10-Bit Addressing with Address or Data Hold 28.2.3.7. Client Transmission 28.2.3.7.1. Client Mode Bus Collision 28.2.3.7.2. 7-Bit Transmission 28.2.3.7.3. 7-Bit Transmission with Address Hold Enabled 28.2.4. I2C Host Mode 28.2.4.1. I2C Host Mode Operation 28.2.4.1.1. Clock Arbitration 28.2.4.1.2. WCOL Status Flag 28.2.4.1.3. I2C Host Mode Start Condition Timing 28.2.4.1.4. I2C Host Mode Repeated Start Condition Timing 28.2.4.1.5. Acknowledge Sequence Timing 28.2.4.1.5.1. Acknowledge Write Collision 28.2.4.1.6. Stop Condition Timing 28.2.4.1.6.1. Write Collision on Stop 28.2.4.1.7. Sleep Operation 28.2.4.1.8. Effects of a Reset 28.2.4.2. I2C Host Mode Transmission 28.2.4.2.1. BF Status Flag 28.2.4.2.2. WCOL Status Flag 28.2.4.2.3. ACKSTAT Status Flag 28.2.4.2.4. Typical Transmit Sequence 28.2.4.3. I2C Host Mode Reception 28.2.4.3.1. BF Status Flag 28.2.4.3.2. SSPOV Status Flag 28.2.4.3.3. WCOL Status Flag 28.2.4.3.4. Typical Receive Sequence 28.2.5. Multi-Host Mode 28.2.5.1. Multi-Host Communication, Bus Collision and Bus Arbitration 28.2.5.1.1. Bus Collision During a Start Condition 28.2.5.1.2. Bus Collision During a Repeated Start Condition 28.2.5.1.3. Bus Collision During a Stop Condition 28.3. Baud Rate Generator 28.4. Register Definitions: MSSP Control 28.4.1. SSPxBUF 28.4.2. SSPxADD 28.4.3. SSPxMSK 28.4.4. SSPxSTAT 28.4.5. SSPxCON1 28.4.6. SSPxCON2 28.4.7. SSPxCON3 28.5. Register Summary - MSSP Control 29. FVR - Fixed Voltage Reference 29.1. Independent Gain Amplifiers 29.2. FVR Stabilization Period 29.3. Register Definitions: FVR 29.3.1. FVRCON 29.4. Register Summary - FVR 30. ADC - Analog-to-Digital Converter 30.1. ADC Configuration 30.1.1. Port Configuration 30.1.2. Channel Selection 30.1.3. ADC Voltage Reference 30.1.4. Conversion Clock 30.1.5. Interrupts 30.1.6. ADC Result Formatting 30.2. ADC Operation 30.2.1. Starting a Conversion 30.2.2. Completion of a Conversion 30.2.3. ADC Operation During Sleep 30.2.3.1. External Trigger During Sleep 30.2.4. Auto-Conversion Trigger 30.2.5. ADC Conversion Procedure 30.3. ADC Acquisition Requirements 30.4. Register Definitions: ADC Control 30.4.1. ADCON0 30.4.2. ADCON1 30.4.3. ADACT 30.4.4. ADRES 30.5. Register Summary - ADC 31. Charge Pump 31.1. Manually Enabled 31.2. Automatically Enabled 31.3. Disabled 31.4. Charge Pump Threshold 31.5. Charge Pump Ready 31.6. Register Definitions: Charge Pump 31.6.1. CPCON 32. Instruction Set Summary 32.1. Read-Modify-Write Operations 32.2. Standard Instruction Set 32.2.1. Standard Instruction Set 33. ICSP™ - In-Circuit Serial Programming™ 33.1. High-Voltage Programming Entry Mode 33.2. Low-Voltage Programming Entry Mode 33.3. Common Programming Interfaces 34. Register Summary 35. Electrical Specifications 35.1. Absolute Maximum Ratings(†) 35.2. Standard Operating Conditions 35.3. DC Characteristics 35.3.1. Supply Voltage 35.3.2. Supply Current (IDD)(1,2) 35.3.3. Power-Down Current (IPD)(1,2,3) 35.3.4. I/O Ports 35.3.5. Memory Programming Specifications 35.3.6. Thermal Characteristics 35.4. AC Characteristics 35.4.1. External Clock/Oscillator Timing Requirements 35.4.2. Internal Oscillator Parameters(1) 35.4.3. I/O and CLKOUT Timing Specifications 35.4.4. Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications 35.4.5. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 35.4.6. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 35.4.7. Fixed Voltage Reference (FVR) Specifications 35.4.8. Timer0 and Timer1 External Clock Requirements 35.4.9. Capture/Compare/PWM Requirements (CCP) 35.4.10. EUSART Synchronous Transmission Requirements 35.4.11. EUSART Synchronous Receive Requirements 35.4.12. SPI Mode Requirements 35.4.13. I2C Bus Start/Stop Bits Requirements 35.4.14. I2C Bus Data Requirements 36. DC and AC Characteristics Graphs and Tables 36.1. Analog-to-Digital Converter (10-bit) Graphs 36.2. Band Gap Ready Graphs 36.3. Brown-Out Reset Graphs 36.4. Fixed Voltage Reference Graphs 36.5. HFINTOSC Error Graphs 36.6. HFINTOSC Wake From Sleep Graphs 36.7. I/O Rise/Fall Times Graphs 36.8. IDD Graphs 36.9. Input Buffer Graphs 36.10. IPD Graphs 36.11. LFINTOSC Graphs 36.12. OSCTUNE Graphs 36.13. Power-On Reset Graphs 36.14. VOH - VOL Graphs 36.15. Watchdog Timer Graphs 36.16. Weak Pull-Up Graphs 37. Packaging Information 37.1. Package Details 38. Appendix A: Revision History 39. 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