The ADC can generate the following events:

Table 1. Event Generators in ADC
Generator Name Description Event Type Generating Clock Domain Length of Event
Peripheral Event
ADCn RESRDY Result ready Pulse CLK_PER One clock period

The conditions for generating an event are identical to those that will raise the corresponding flag in the Interrupt Flags (ADCn.INTFLAGS) register.

The ADC has one event user for detecting and acting upon input events. The table below describes the event user and the associated functionality.

Table 2. Event Users and Available Event Actions in ADC
User Name Description Input Detection Async/Sync
Peripheral Input
ADCn START ADC start conversion Edge Async

The ADC can be configured to start a conversion on the rising edge of an event signal by writing a ‘1’ to the STARTEI bit field in the Event Control (ADCn.EVCTRL) register. Refer to the EVSYS - Event System section for more details regarding event types and Event System configuration.

When an input event trigger occurs, the positive edge will be detected, the Start Conversion (STCONV) bit in the Command (ADCn.COMMAND) register will be set, and the conversion will start. When the conversion is completed, the Result Ready (RESRDY) flag in the Interrupt Flags (ADCn.INTFLAGS) register is set and the STCONV bit in ADCn.COMMAND is cleared.