Control Register E Clear - Split Mode

Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.

Name:
CTRLECLR
Offset:
0x04
Reset:
0x00
Access:
-
Bit76543210
CMD[1:0]CMDEN[1:0]
AccessR/WR/WR/WR/W
Reset0000

Bits 3:2 – CMD[1:0]: Command

Command

This bit field is used for software control of restart and reset of the timer/counter. The command bit field always reads as ‘0’.

ValueNameDescription
0x0 NONE No command
0x1 - Reserved
0x2 RESTART Force restart
0x3 RESET Force hard Reset (ignored if the timer/counter is enabled)

Bits 1:0 – CMDEN[1:0]: Command Enable

Command Enable

This bit field configures what timer/counters the command given by the CMD-bits will apply to.

ValueNameDescription
0x0 NONE None
0x1 - Reserved
0x2 - Reserved
0x3 BOTH Command (CMD) will apply to both low byte and high byte timer/counter