I/O Pins

Table 1. I/O Pin Specifications(1)
Symbol Description Min. Typ.✝ Max. Unit Conditions
Input Low Voltage
VIL I/O PORT:
  • with Schmitt Trigger buffer
0.2×VDD V  
  • with I2C levels
0.3×VDD V  
  • with SMBus 3.0 levels
0.8 V  
RESET pin 0.2×VDD V  
Input High Voltage
VIH I/O PORT:
  • with Schmitt Trigger buffer
0.8×VDD V  
  • with I2C levels
0.7×VDD V  
  • with SMBus 3.0 levels
1.35 V

0°C ≤ TA ≤ +125°C,

2.5V ≤ VDD ≤ 5.5V

1.45 V  
RESET pin 0.8×VDD V  
Input Leakage Current(2)
IIL I/O PORTS ±5 ±125 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

±5 ±1000 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 125°C

RESET pin(3) ±50 ±200 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

Pull-up Current
IPUR   150 200 μA VDD = 3.0V, VPIN = GND
Output Low Voltage
VOL Standard I/O ports 0.6 V IOL = 10 mA, VDD = 3.0V
Output High Voltage
VOH Standard I/O ports VDD-0.7 V IOH = 6 mA, VDD = 3.0V
I/O Slew Rate
  Rising slew rate 45 ns PORTCTRL.SRL = 0x01
Rising slew rate 22 ns PORTCTRL.SRL = 0x00
Falling slew rate 30 ns PORTCTRL.SRL = 0x01
Falling slew rate 16 ns PORTCTRL.SRL = 0x00
Pin Capacitance
CIO All I/O pins 5 pF  

Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Notes:
  1. 1.These figures are valid for all I/O ports regardless of if they are connected to the VDD or VDDIO2 power domain.
  2. 2.The negative current is defined as the current sourced by the pin.
  3. 3.The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may occur at different input voltages.