Main Clock Selection and Prescaler

All available oscillators and the external clock (EXTCLK) can be used as the main clock source for the Main Clock (CLK_MAIN). The main clock source is selectable from software and can be safely changed during normal operation.

The Configuration Change Protection mechanism prevents unsafe clock switching. For more details, refer to the Configuration Change Protection (CCP) section.

The Clock Failure Detection mechanism ensures safe switching to an internal clock source upon clock failure when enabled.

Upon the selection of an external clock source, a switch to the chosen clock source will occur only if edges are detected. Until a sufficient number of clock edges are detected, the switch will not occur, and it will not be possible to change to another clock source again without executing a Reset.

An ongoing clock source switch is indicated by the Main Clock Oscillator Changing (SOSC) bit in the Main Clock Status (CLKCTRL.MCLKSTATUS) register. The stability of the external clock sources is indicated by the respective Status (EXTS and XOSC32KS) bits in CLKCTRL.MCLKSTATUS.

CAUTION: If an external clock source fails while used as the CLK_MAIN source, the clock source will default to the start-up clock source only if the CFD is enabled. If the CFD is not enabled, only the Watchdog Timer (WDT) can provide a System Reset. For more details, refer to the Clock Failure Detection (CFD) section.

The CLK_MAIN is fed into the prescaler before being used by the peripherals (CLK_PER) in the device. The prescaler divides CLK_MAIN by a factor from 1 to 64.

Figure 1. Main Clock and Prescaler