When the external voltage source is sinusoidal, the effects of the
Z_{CPINV} offset can be eliminated by isolating the external voltage source from
the ZCD input pin with a capacitor in series with the current-limiting resistor, as shown
in the figure below.

Figure 1. AC Coupling the ZCD

The phase shift resulting from the capacitor will cause the ZCD output to switch in advance of the actual zero-crossing event. The phase shift will be the same for both rising and falling zero-crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means or selecting a capacitor value large enough that the phase shift is negligible.

To determine the series resistor and capacitor values for this
configuration, start by computing the impedance, Z, to obtain a peak current of
I_{ZCD_MAX}/2. Next, select a suitably large non-polarized capacitor and compute
its reactance, X_{C}, at the external voltage source frequency. Finally, compute
the series resistor (R_{SERIES}), capacitor peak voltage, and phase shift by using
the formulas shown below.

When this technique is used, and the input signal is not present, the ZCD may oscillate. Oscillation can be prevented by connecting the ZCD input pin to ground with a high-value resistor such as 200 kΩ, but this resistor will introduce an offset in the detection of the zero-cross event.

Figure 2. R-C Equations

V_{PEAK} = External voltage source peak voltage

f = External voltage source frequency

C = Series capacitor

R = Series resistor

V_{C} = Peak capacitor voltage

Φ = Capacitor-induced zero-crossing phase advance in radians

T_{Φ} = Time zero-cross event occurs before actual
zero-crossing

Figure 3. R-C Calculation Example