ASI Control A

Name:
ASI_CTRLA
Offset:
0x09
Reset:
0x03
Access:
-
Bit76543210
UPDICLKSEL[1:0]
AccessR/WR/W
Reset11

Bits 1:0 – UPDICLKSEL[1:0]: UPDI Clock Divider Select

UPDI Clock Divider Select

Writing these bits selects the UPDI clock output frequency. The default setting after Reset and enable is 4 MHz. See the Electrical Characteristics section for more information on possible UPDI oscillator frequencies.

ValueDescription
0x0 (reserved)
0x1 16 MHz UPDI clock
0x2 8 MHz UPDI clock
0x3 4 MHz UPDI clock (default setting)