Testing the CFD and Changing the Main Clock to the Start-Up Clock Source

If the Clock Failure Detection Source (CFDSRC) bit field in the Main Clock Control C (CLKCTRL.MCLKCTRLC) register has the value 0x0 and the main clock is monitored, writing a ‘1’ to the Clock Failure Detection Test (CDFTST) bit in MCLKCTRLC will trigger a fault that will change the main clock to the start-up clock source.