Contents

Introduction Features 1. Pin Functionality Difference 1.1. Additional Pin Functionalities 1.2. Alternate Pin Configuration 2. Enhancement and Additional Features in ATmega324PB 2.1. PTC - Peripheral Touch Controller 2.1.1. PTC Functional Description 2.2. CFD - Clock Failure Detection Mechanism 2.3. OCM1C2 - Output Compare Modulator 2.4. USART 2.5. Analog Comparator 2.6. Unique Device ID 2.7. Additional SPI 2.8. Additional TWI 2.9. Additional Timer/Counters 3. Updated Features 3.1. Full Swing Oscillator 3.2. NVM 3.3. Signature 4. Register Description 4.1. PINE – Port E Input Pins Address 4.2. DDRE – Port E Data Direction Register 4.3. PORTE – Port E Data Register 4.4. XFDCSR – XOSC Failure Detection Control and Status Register 4.5. UCSRD – USART Control and Status Register D 4.6. ACSRB – Analog Comparator Control and Status Register 4.7. Serial Number Byte 8 to 0 5. Revision History 6. Legal Disclaimer