The following table lists the Two-Port Large SRAM signals in the generated macro.
Port | Direction | Default Polarity | Description |
---|---|---|---|
CLK |
In |
Rising Edge |
Single clock to drive both WCLK and RCLK. |
WD[] |
In |
Write data. |
|
WADDR[] |
In |
Write address. |
|
WEN |
In |
Active high |
Write port enable. |
WCLK |
In |
Rising edge |
Write clock. |
RCLK |
In |
Rising edge |
Read clock. |
REN |
In |
Active high |
Read data enable. |
RADDR[] |
In |
Read address. |
|
RD[] |
Out |
Read data. |
|
RD_EN |
In |
Active high |
Read data register enable. |
RD_SRST_N |
In |
Active low |
Read data register Synchronous reset. |
ARST_N |
In |
Active low |
Read data register Asynchronous reset. |
SB_CORRECT |
Out |
Active High |
Single-bit correct flag. |
DB_DETECT |
Out |
Active High |
Double-bit detect flag. |
WBYTE_EN[] |
In |
Active High |
Write Byte Enables (per byte). |