Getting Started

The Memory Log Analyzer is a GUI-based tool that analyzes the debug log generated while training the memory interface. When the log file is provided as input to the tool, it analyzes the log and reports if the training is passed or failed. If the training fails, the analyzer supplies a probable reason for failure and action required to ensure that the training passes. Currently, this tool supports analysis of the MSS LPDDR4 training log for the PolarFire® SoC FPGA.

The Memory Log Analyzer GUI supports LPDDR4 memory controller for the PolarFire SoC FPGA Device. On the PolarFire SoC device, the LPDDR4 memory initialization is carried out by the software running on the CoreComplex. While the training is in progress, the software logs intermediate debug information on the UART serial terminal. Ensure that you save the serial terminal messages as a text file. This file serves as the log file input to the analyzer tool. Browse and select the log file to view the results. If the training fails, see Troubleshooting.

For information about how to enable UART terminal and how to export the log as a text file, see PolarFire SoC Quickstart Card .

Important:

By default, the DDR initialization debug log is not enabled in the software. Ensure to enable the debug log in the software that you are running. It can either be a BareMetal software SoftConsole project or the Hart Software Services (HSS) project. For information on how to enable the DDR initialization debug log, see Enable DDR Debugging.
When debugging a DDR interface, it is recommended to use the BareMetal DDR example. Download the example source files from the DDR Demo on PolarFire SoC (mpfs-hal-ddr-demo) GitHub repository.

Additional Reference

SmartDebug supports training analysis of PolarFire fabric memory interfaces, which use memory controller IP generated by Libero SoC software. For more information, see SmarDebug User Guide.

Important: The most up-to-date version of this document is available at this location: Memory Log Analyzer.