When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD
and ST instructions, 0x20 must be added to these offset addresses.
Note: 1. This register contains interrupt control bits for several Timer/Counters, but
only Timer1 bits are described in this section. The remaining bits are described in
their respective timer sections.
Timer/Counter1,
Input Capture Interrupt Enable
When this bit is
written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding
Interrupt Vector (see
Interrupts) is executed when the ICF1 Flag, located in TIFR, is
set.
Timer/Counter1,
Output Compare A Match Interrupt Enable
When this bit is
written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The
corresponding Interrupt Vector (see
Interrupts) is executed when the OCF1A Flag, located in TIFR, is
set.
Timer/Counter1,
Output Compare B Match Interrupt Enable
When this bit is
written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The
corresponding Interrupt Vector (see
Interrupts) is executed when the OCF1B Flag, located in TIFR, is
set.
Timer/Counter1,
Overflow Interrupt Enable
When this bit is
written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding
Interrupt Vector (see
Interrupts) is executed when the TOV1 Flag, located in TIFR, is
set.