When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD
and ST instructions, 0x20 must be added to these offset addresses.
Interrupt Sense
Control 1 Bit 1 and Bit 0 [n = 1:0]
The External Interrupt
1 is activated by the external pin INT1 if the SREG I-bit and the corresponding
interrupt mask in the GICR are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in the next table. The value on the INT1 pin is
sampled before detecting edges. If edge or toggle interrupt is selected, pulses that
last longer than one clock period will generate an interrupt. Shorter pulses are not
guaranteed to generate an interrupt. If low level interrupt is selected, the low level
must be held until the completion of the currently executing instruction to generate an
interrupt.
Table 1. Interrupt 1 Sense
Control
ISC11 |
ISC10 |
Description |
0 |
0 |
The low level of
INT1 generates an interrupt request. |
0 |
1 |
Any logical
change on INT1 generates an interrupt request. |
1 |
0 |
The falling edge
of INT1 generates an interrupt request. |
1 |
1 |
The rising edge
of INT1 generates an interrupt request. |
Interrupt Sense
Control 0 Bit 1 and Bit 0 [n = 1:0]
The External Interrupt
0 is activated by the external pin INT0 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in the next table. The value on the INT0 pin is sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than
one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held
until the completion of the currently executing instruction to generate an interrupt.
Table 2. Interrupt 0 Sense
Control
ISC01 |
ISC00 |
Description |
0 |
0 |
The low level of
INT0 generates an interrupt request. |
0 |
1 |
Any logical
change on INT0 generates an interrupt request. |
1 |
0 |
The falling edge
of INT0 generates an interrupt request. |
1 |
1 |
The rising edge of
INT0 generates an interrupt request. |