ADCSRA – ADC Control and Status Register A
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADEN | ADSC | ADFR | ADIF | ADIE | ADPSn[2:0] | ||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
ADC Enable
ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.
ADC Free Running Select
ADC Interrupt Flag
ADC Interrupt Enable
ADC Prescaler Select [n = 2:0]
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
ADPS[2:0] | Division Factor |
---|---|
000 | 2 |
001 | 2 |
010 | 4 |
011 | 8 |
100 | 16 |
101 | 32 |
110 | 64 |
111 | 128 |