8-bit AVR Microcontroller

EECR – The EEPROM Control Register

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.

Name:
EECR
Offset:
0x1C
Reset:
0x00
Access:
When addressing I/O Registers as data space the offset address is 0x3C
Bit76543210
EERIEEEMWEEEWEEERE
AccessR/WR/WR/WR/W
Reset00x0

Bit 3 – EERIE: EEPROM Ready Interrupt Enable

EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

Bit 2 – EEMWE: EEPROM Master Write Enable

EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

Bit 1 – EEWE: EEPROM Write Enable

EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

  1. 1.Wait until EEWE becomes zero.
  2. 2.Wait until SPMEN in SPMCR becomes zero.
  3. 3.Write new EEPROM address to EEAR (optional).
  4. 4.Write new EEPROM data to EEDR (optional).
  5. 5.Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
  6. 6.Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See Boot Loader Support – Read-While-Write Self-Programming for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

Bit 0 – EERE: EEPROM Read Enable

EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. The following table lists the typical programming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles(1) Typ Programming Time
EEPROM Write (from CPU) 8448 8.5ms
Note: 1. Uses 1MHz clock, independent of CKSEL Fuse settings.

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example
EEPROM_write:
   ; Wait for completion of previous write
   sbic EECR,EEWE
   rjmp EEPROM_write
   ; Set up address (r18:r17) in address register
   out EEARH, r18
   out EEARL, r17
   ; Write data (r16) to data register
   out EEDR,r16
   ; Write logical one to EEMWE
   sbi EECR,EEMWE
   ; Start eeprom write by setting EEWE
   sbi EECR,EEWE
   ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
   /* Wait for completion of previous write */
   while(EECR & (1<<EEWE))
   ;
   /* Set up address and data registers */
   EEAR = uiAddress;
   EEDR = ucData;
   /* Write logical one to EEMWE */
   EECR |= (1<<EEMWE);
   /* Start eeprom write by setting EEWE */
   EECR |= (1<<EEWE);
}

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example
EEPROM_read:
   ; Wait for completion of previous write
   sbic EECR,EEWE
   rjmp EEPROM_read
   ; Set up address (r18:r17) in address register
   out EEARH, r18
   out EEARL, r17
   ; Start eeprom read by writing EERE
   sbi EECR,EERE
   ; Read data from data register
   in r16,EEDR
   ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
   /* Wait for completion of previous write */
   while(EECR & (1<<EEWE))
   ;
   /* Set up address register */
   EEAR = uiAddress;
   /* Start eeprom read by writing EERE */
   EECR |= (1<<EERE);
   /* Return data from data register */
   return EEDR;
}