Two-wire Serial Interface Characteristics

The table below describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8A Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 30-3.

Table 1. Two-wire Serial Bus Requirements
Symbol	Parameter	Condition	Min	Max	Units
V_IL	Input Low-voltage		-0.5	0.3V_CC	V
V_IH	Input High-voltage		0.7V_CC	V_CC + 0.5	V
V_hys⁽¹⁾	Hysteresis of Schmitt Trigger Inputs		0.05V_CC⁽²⁾	–	V
V_OL⁽¹⁾	Output Low-voltage	3mA sink current	0	0.4	V
t_r⁽¹⁾	Rise Time for both SDA and SCL		20 + 0.1C_b⁽³⁾⁽²⁾	300	ns
t_of⁽¹⁾	Output Fall Time from V_IHmin to V_ILmax	10pF < C_b < 400pF⁽³⁾	20 + 0.1C_b⁽³⁾⁽²⁾	250	ns
t_SP⁽¹⁾	Spikes Suppressed by Input Filter		0	50⁽²⁾	ns
I_i	Input Current each I/O Pin	0.1V_CC < V_i < 0.9V_CC	-10	10	μA
C_i⁽¹⁾	Capacitance for each I/O Pin		–	10	pF
f_SCL	SCL Clock Frequency	f_CK⁽⁴⁾ > max(16f_SCL, 250kHz)⁽⁵⁾	0	400	kHz
Rp	Value of Pull-up resistor	f_SCL ≤ 100kHz	VCC−0.4V3mA	1000nsCb	Ω
Rp	Value of Pull-up resistor	f_SCL > 100kHz	VCC−0.4V3mA	300nsCb	Ω
t_HD;STA	Hold Time (repeated) START Condition	f_SCL ≤ 100kHz	4.0	–	μs
t_HD;STA	Hold Time (repeated) START Condition	f_SCL > 100kHz	0.6	–	μs
t_LOW	Low Period of the SCL Clock	f_SCL ≤ 100kHz⁽⁶⁾	4.7	–	μs
t_LOW	Low Period of the SCL Clock	f_SCL > 100kHz⁽⁷⁾	1.3	–	μs
t_HIGH	High period of the SCL clock	f_SCL ≤ 100kHz	4.0	–	μs
t_HIGH	High period of the SCL clock	f_SCL > 100kHz	0.6	–	μs
t_SU;STA	Set-up time for a repeated START condition	f_SCL ≤ 100kHz	4.7	–	μs
t_SU;STA	Set-up time for a repeated START condition	f_SCL > 100kHz	0.6	–	μs
t_HD;DAT	Data hold time	f_SCL ≤ 100kHz	0	3.45	μs
t_HD;DAT	Data hold time	f_SCL > 100kHz	0	0.9	μs
t_SU;DAT	Data setup time	f_SCL ≤ 100kHz	250	–	ns
t_SU;DAT	Data setup time	f_SCL > 100kHz	100	–	ns
t_SU;STO	Setup time for STOP condition	f_SCL ≤ 100kHz	4.0	–	μs
t_SU;STO	Setup time for STOP condition	f_SCL > 100kHz	0.6	–	μs
t_BUF	Bus free time between a STOP and START condition	f_SCL ≤ 100kHz	4.7	–	μs
t_BUF	Bus free time between a STOP and START condition	f_SCL > 100kHz	1.3	–	μs

Notes:

1.In ATmega8A, this parameter is characterized and not 100% tested.
2.Required only for f_SCL > 100kHz.
3.C_b = capacitance of one bus line in pF.
4.f_CK = CPU clock frequency
5.This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general f_SCL requirement.
6.The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/f_SCL - 2/f_CK), thus f_CK must be greater than 6MHz for the low time requirement to be strictly met at f_SCL = 100kHz.
7.The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/f_SCL - 2/f_CK), thus the low time requirement will not be strictly met for f_SCL > 308kHz when f_CK = 8MHz. Still, ATmega8A devices connected to the bus may communicate at full speed (400kHz) with other ATmega8A devices, as well as any other device with a proper t_LOW acceptance margin.

Figure 1. Two-wire Serial Bus Timing

8-bit AVR Microcontroller

Two-wire Serial Interface Characteristics