Contents

Introduction Family Overview 2.1. Memory Overview 2.2. Peripheral Overview Features 4. Block Diagram 5. Pinout 5.1. 28-pin SPDIP and SSOP 5.2. 28-pin VQFN 5.3. 32-pin VQFN and TQFP 5.4. 48-pin VQFN and TQFP 6. I/O Multiplexing and Considerations 6.1. I/O Multiplexing 7. Hardware Guidelines 7.1. General Guidelines 7.1.1. Special Consideration for Packages with Center Pad 7.2. Connection for Power Supply 7.2.1. Digital Power Supply 7.3. Connection for RESET 7.4. Connection for UPDI Programming 7.4.1. UPDI Connection v1 7.4.2. UPDI Connection v2 7.5. Connecting External Crystal Oscillators 7.5.1. Connection for XTAL32K (External 32.768 kHz Crystal Oscillator) 7.5.2. Connection for XTALHF (External HF Crystal Oscillator) 7.6. Connection for External Voltage Reference 8. Power Domains 8.1. Power-Up 9. Conventions 9.1. Numerical Notation 9.2. Memory Size and Type 9.3. Frequency and Time 9.4. Registers and Bits 9.4.1. Addressing Registers from Header Files 9.5. ADC Parameter Definitions 10. AVR CPU 10.1. Features 10.2. Overview 10.3. Architecture 10.3.1. Arithmetic Logic Unit (ALU) 10.3.1.1. Hardware Multiplier 10.4. Functional Description 10.4.1. Program Flow 10.4.2. Instruction Execution Timing 10.4.3. Status Register 10.4.4. Stack and Stack Pointer 10.4.5. Register File 10.4.5.1. The X-, Y-, and Z-Registers 10.4.6. Configuration Change Protection (CCP) 10.4.6.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 10.4.6.2. Sequence for Execution of Self-Programming 10.4.7. On-Chip Debug Capabilities 10.5. Register Summary 10.6. Register Description 10.6.1. CCP 10.6.2. SP 10.6.3. SREG 11. Memories 11.1. Overview 11.2. Memory Map 11.3. In-System Reprogrammable Flash Program Memory 11.4. SRAM Data Memory 11.5. EEPROM Data Memory 11.6. USERROW - User Row 11.7. LOCK - Memory Sections Access Protection 11.7.1. Lock Summary 11.7.2. Lock Description 11.7.2.1. Lock Key 11.8. FUSE - Configuration and User Fuses 11.8.1. Fuse Summary 11.8.2. Fuse Description 11.8.2.1. Watchdog Configuration 11.8.2.2. Brown-Out Detector Configuration 11.8.2.3. Oscillator Configuration 11.8.2.4. System Configuration 0 11.8.2.5. System Configuration 1 11.8.2.6. Code Size 11.8.2.7. Boot Size 11.9. SIGROW - Signature Row 11.9.1. Signature Row Summary 11.9.2. Signature Row Description 11.9.2.1. Device ID n 11.9.2.2. Temperature Sensor Calibration n 11.9.2.3. Serial Number Byte n 11.10. I/O Memory 11.10.1. Accessing 16-Bit Registers 11.10.2. Accessing 24-and 32-Bit Registers 12. GPR - General Purpose Registers 12.1. Register Summary 12.2. Register Description 12.2.1. General Purpose Register n 13. Peripherals and Architecture 13.1. Peripheral Address Map 13.2. Interrupt Vector Mapping 13.3. SYSCFG - System Configuration 13.3.1. Register Summary 13.3.2. Register Description 13.3.2.1. Device Revision ID 14. NVMCTRL - Nonvolatile Memory Controller 14.1. Features 14.2. Overview 14.2.1. Block Diagram 14.3. Functional Description 14.3.1. Memory Organization 14.3.1.1. Flash 14.3.1.1.1. Physical Sections 14.3.1.1.2. Logical Sections 14.3.1.1.3. Flash Access Protections 14.3.1.2. EEPROM 14.3.1.3. User Row 14.3.1.4. Fuses 14.3.1.5. Signature Row 14.3.2. Memory Access 14.3.2.1. Read 14.3.2.2. Page Buffer Load 14.3.2.3. Programming 14.3.2.4. Command Modes 14.3.2.4.1. Page Write Command 14.3.2.4.2. Page Erase Command 14.3.2.4.3. Flash Multi-Page Erase Mode 14.3.2.4.4. Page Erase/Write Operation 14.3.2.4.5. Page Buffer Clear Commands 14.3.2.4.6. EEPROM Erase Command 14.3.3. Preventing Flash/EEPROM Corruption 14.3.4. Interrupts 14.3.5. Sleep Mode Operation 14.3.6. Configuration Change Protection 14.4. Register Summary 14.5. Register Description 14.5.1. Control A 14.5.2. Control B 14.5.3. Interrupt Control 14.5.4. Interrupt Flags 14.5.5. Status 14.5.6. Data 14.5.7. Address 15. CLKCTRL - Clock Controller 15.1. Features 15.2. Overview 15.2.1. Block Diagram - CLKCTRL 15.2.2. Signal Description 15.3. Functional Description 15.3.1. Initialization 15.3.2. Main Clock Selection and Prescaler 15.3.3. Main Clock After Reset 15.3.4. Clock Sources 15.3.4.1. Internal Oscillators 15.3.4.1.1. Internal High-Frequency Oscillator (OSCHF) 15.3.4.1.2. 32.768 kHz Oscillator (OSC32K) 15.3.4.2. External Clock Sources 15.3.4.2.1. High-Frequency Crystal Oscillator (XOSCHF) 15.3.4.2.2. 32.768 kHz Crystal Oscillator (XOSC32K) 15.3.5. Clock Failure Detection (CFD) 15.3.5.1. Clock Failure Detection (CFD) Operation 15.3.5.2. Condition Clearing 15.3.5.3. CFD Test 15.3.5.3.1. Testing the CFD Without Influencing the Main Clock 15.3.5.3.2. Testing the CFD and Changing the Main Clock to the Start-Up Clock Source 15.3.6. Timebase 15.3.7. Manual Tuning and Autotune 15.3.8. Sleep Mode Operation 15.3.9. Configuration Change Protection 15.4. Register Summary 15.5. Register Description 15.5.1. Main Clock Control A 15.5.2. Main Clock Control B 15.5.3. Main Clock Control C 15.5.4. Main Clock Interrupt Control 15.5.5. Main Clock Interrupt Flags 15.5.6. Main Clock Status 15.5.7. Timebase 15.5.8. Internal High-Frequency Oscillator Control A 15.5.9. Internal High-Frequency Oscillator Frequency Tune 15.5.10. 32.768 kHz Oscillator Control A 15.5.11. 32.768 kHz Crystal Oscillator Control A 15.5.12. External High-Frequency Oscillator Control A 16. SLPCTRL - Sleep Controller 16.1. Features 16.2. Overview 16.2.1. Block Diagram 16.3. Functional Description 16.3.1. Initialization 16.3.2. Operation 16.3.2.1. Sleep Modes 16.3.2.2. Wake-up Time 16.3.3. Debug Operation 16.4. Register Summary 16.5. Register Description 16.5.1. Control A 17. RSTCTRL - Reset Controller 17.1. Features 17.2. Overview 17.2.1. Block Diagram 17.2.2. Signal Description 17.3. Functional Description 17.3.1. Initialization 17.3.2. Operation 17.3.2.1. Reset Sources 17.3.2.1.1. Power-on Reset (POR) 17.3.2.1.2. Brown-out Detector (BOD) Reset 17.3.2.1.3. External Reset 17.3.2.1.4. Watchdog Reset 17.3.2.1.5. Software Reset (SWRST) 17.3.2.1.6. Unified Program and Debug Interface (UPDI) Reset 17.3.2.1.7. High Voltage (HV) Pulse 17.3.2.1.8. Domains Affected By Reset 17.3.2.2. Reset Time 17.3.3. Sleep Mode Operation 17.3.4. Configuration Change Protection 17.4. Register Summary 17.5. Register Description 17.5.1. Reset Flag Register 17.5.2. Software Reset Register 18. CPUINT - CPU Interrupt Controller 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.3. Functional Description 18.3.1. Initialization 18.3.2. Operation 18.3.2.1. Enabling, Disabling and Resetting 18.3.2.2. Interrupt Vector Locations 18.3.2.3. Interrupt Response Time 18.3.2.4. Interrupt Priority 18.3.2.4.1. Non-Maskable Interrupts 18.3.2.4.2. High-Priority Interrupt 18.3.2.4.3. Normal-Priority Interrupts 18.3.2.4.3.1. Static Scheduling 18.3.2.4.3.2. Modified Static Scheduling 18.3.2.4.3.3. Round Robin Scheduling 18.3.2.5. Compact Vector Table 18.3.3. Debug Operation 18.3.4. Configuration Change Protection 18.4. Register Summary 18.5. Register Description 18.5.1. Control A 18.5.2. Status 18.5.3. Interrupt Priority Level 0 18.5.4. Interrupt Vector with Priority Level 1 19. EVSYS - Event System 19.1. Features 19.2. Overview 19.2.1. Block Diagram 19.2.2. Signal Description 19.3. Functional Description 19.3.1. Initialization 19.3.2. Operation 19.3.2.1. Event User Multiplexer Setup 19.3.2.2. Event System Channel 19.3.2.3. Event Generators 19.3.2.4. Event Users 19.3.2.5. Synchronization 19.3.2.6. Software Event 19.3.3. Sleep Mode Operation 19.3.4. Debug Operation 19.4. Register Summary 19.5. Register Description 19.5.1. Software Events 19.5.2. Channel n Generator Selection 19.5.3. User Channel MUX 20. PORTMUX - Port Multiplexer 20.1. Overview 20.2. Register Summary 20.3. Register Description 20.3.1. EVSYS Pin Position 20.3.2. CCL LUTn Pin Position 20.3.3. USARTn Pin Position 20.3.4. USARTn Pin Position 20.3.5. SPIn Pin Position 20.3.6. TWI Pin Positions 20.3.7. TCAn Pin Position 20.3.8. TCBn Pin Position 20.3.9. ACn Pin Position 21. PORT - I/O Pin Configuration 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.2.2. Signal Description 21.3. Functional Description 21.3.1. Initialization 21.3.2. Operation 21.3.2.1. Basic Functions 21.3.2.2. Port Configuration 21.3.2.3. Pin Configuration 21.3.2.4. Multi-Pin Configuration 21.3.2.5. Virtual Ports 21.3.2.6. Peripheral Override 21.3.3. Interrupts 21.3.3.1. Asynchronous Sensing Pin Properties 21.3.4. Events 21.3.5. Sleep Mode Operation 21.3.6. Debug Operation 21.4. Register Summary - PORTx 21.5. Register Description - PORTx 21.5.1. Data Direction 21.5.2. Data Direction Set 21.5.3. Data Direction Clear 21.5.4. Data Direction Toggle 21.5.5. Output Value 21.5.6. Output Value Set 21.5.7. Output Value Clear 21.5.8. Output Value Toggle 21.5.9. Input Value 21.5.10. Interrupt Flags 21.5.11. Port Control 21.5.12. Multi-Pin Configuration 21.5.13. Multi-Pin Control Update Mask 21.5.14. Multi-Pin Control Set Mask 21.5.15. Multi-Pin Control Clear Mask 21.5.16. Pin n Control 21.5.17. Event Generator Control A 21.6. Register Summary - VPORTx 21.7. Register Description - VPORTx 21.7.1. Data Direction 21.7.2. Output Value 21.7.3. Input Value 21.7.4. Interrupt Flags 22. BOD - Brown-out Detector 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.3. Functional Description 22.3.1. Initialization 22.3.2. Interrupts 22.3.3. Sleep Mode Operation 22.3.4. Configuration Change Protection 22.4. Register Summary 22.5. Register Description 22.5.1. Control A 22.5.2. Control B 22.5.3. VLM Control 22.5.4. Interrupt Control 22.5.5. VLM Interrupt Flags 22.5.6. VLM Status 23. VREF - Voltage Reference 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.3. Functional Description 23.3.1. Initialization 23.4. Register Summary 23.5. Register Description 23.5.1. DAC0 Reference 23.5.2. Analog Comparator Reference 24. WDT - Watchdog Timer 24.1. Features 24.2. Overview 24.2.1. Block Diagram 24.3. Functional Description 24.3.1. Initialization 24.3.2. Clocks 24.3.3. Operation 24.3.3.1. Normal Mode 24.3.3.2. Window Mode 24.3.3.3. Preventing Unintentional Changes 24.3.4. Sleep Mode Operation 24.3.5. Debug Operation 24.3.6. Synchronization 24.3.7. Configuration Change Protection 24.4. Register Summary 24.5. Register Description 24.5.1. Control A 24.5.2. Status 25. TCA - 16-bit Timer/Counter Type A 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.2.2. Signal Description 25.3. Functional Description 25.3.1. Definitions 25.3.2. Initialization 25.3.3. Operation 25.3.3.1. Normal Operation 25.3.3.2. Double Buffering 25.3.3.3. Changing the Period 25.3.3.4. Compare Channel 25.3.3.4.1. Waveform Generation 25.3.3.4.2. Frequency (FRQ) Waveform Generation 25.3.3.4.3. Single-Slope PWM Generation 25.3.3.4.4. Dual-Slope PWM Generation 25.3.3.4.5. Port Override for Waveform Generation 25.3.3.5. Timer/Counter Commands 25.3.3.6. Split Mode - Two 8-Bit Timer/Counters 25.3.4. Events 25.3.5. Interrupts 25.3.6. Sleep Mode Operation 25.4. Register Summary - Normal Mode 25.5. Register Description - Normal Mode 25.5.1. Control A - Normal Mode 25.5.2. Control B - Normal Mode 25.5.3. Control C - Normal Mode 25.5.4. Control D - Normal Mode 25.5.5. Control Register E Clear - Normal Mode 25.5.6. Control Register E Set - Normal Mode 25.5.7. Control Register F Clear 25.5.8. Control Register F Set 25.5.9. Event Control 25.5.10. Interrupt Control Register - Normal Mode 25.5.11. Interrupt Flag Register - Normal Mode 25.5.12. Debug Control Register - Normal Mode 25.5.13. Temporary Bits for 16-Bit Access 25.5.14. Counter Register - Normal Mode 25.5.15. Period Register - Normal Mode 25.5.16. Compare n Register - Normal Mode 25.5.17. Period Buffer Register 25.5.18. Compare n Buffer Register 25.6. Register Summary - Split Mode 25.7. Register Description - Split Mode 25.7.1. Control A - Split Mode 25.7.2. Control B - Split Mode 25.7.3. Control C - Split Mode 25.7.4. Control D - Split Mode 25.7.5. Control Register E Clear - Split Mode 25.7.6. Control Register E Set - Split Mode 25.7.7. Interrupt Control Register - Split Mode 25.7.8. Interrupt Flag Register - Split Mode 25.7.9. Debug Control Register - Split Mode 25.7.10. Low Byte Timer Counter Register - Split Mode 25.7.11. High Byte Timer Counter Register - Split Mode 25.7.12. Low Byte Timer Period Register - Split Mode 25.7.13. High Byte Period Register - Split Mode 25.7.14. Compare Register n For Low Byte Timer - Split Mode 25.7.15. High Byte Compare Register n - Split Mode 26. TCB - 16-Bit Timer/Counter Type B 26.1. Features 26.2. Overview 26.2.1. Block Diagram 26.2.2. Signal Description 26.3. Functional Description 26.3.1. Definitions 26.3.2. Initialization 26.3.3. Operation 26.3.3.1. Modes 26.3.3.1.1. Periodic Interrupt Mode 26.3.3.1.2. Time-Out Check Mode 26.3.3.1.3. Input Capture on Event Mode 26.3.3.1.4. Input Capture Frequency Measurement Mode 26.3.3.1.5. Input Capture Pulse-Width Measurement Mode 26.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode 26.3.3.1.7. Single-Shot Mode 26.3.3.1.8. 8-Bit PWM Mode 26.3.3.2. Output 26.3.3.3. 32-Bit Input Capture 26.3.3.4. Noise Canceler 26.3.3.5. Synchronized with Timer/Counter Type A 26.3.4. Events 26.3.5. Interrupts 26.3.6. Sleep Mode Operation 26.4. Register Summary 26.5. Register Description 26.5.1. Control A 26.5.2. Control B 26.5.3. Event Control 26.5.4. Interrupt Control 26.5.5. Interrupt Flags 26.5.6. Status 26.5.7. Debug Control 26.5.8. Temporary Value 26.5.9. Count 26.5.10. Capture/Compare 27. RTC - Real-Time Counter 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.3. Clocks 27.4. RTC Functional Description 27.4.1. Initialization 27.4.1.1. Configure the Clock CLK_RTC 27.4.1.2. Configure RTC 27.4.2. Operation - RTC 27.4.2.1. Enabling and Disabling 27.5. PIT Functional Description 27.5.1. Initialization 27.5.2. Operation - PIT 27.5.2.1. Enabling and Disabling 27.5.2.2. PIT Interrupt Timing 27.6. Crystal Error Correction 27.7. Events 27.8. Interrupts 27.9. Sleep Mode Operation 27.10. Synchronization 27.11. Debug Operation 27.12. Register Summary 27.13. Register Description 27.13.1. Control A 27.13.2. Status 27.13.3. Interrupt Control 27.13.4. Interrupt Flag 27.13.5. Temporary 27.13.6. Debug Control 27.13.7. Crystal Frequency Calibration 27.13.8. Clock Selection 27.13.9. Count 27.13.10. Period 27.13.11. Compare 27.13.12. Periodic Interrupt Timer Control A 27.13.13. Periodic Interrupt Timer Status 27.13.14. PIT Interrupt Control 27.13.15. PIT Interrupt Flag 27.13.16. Periodic Interrupt Timer Debug Control 27.13.17. Periodic Timer Event Generation Control A 28. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.2.2. Signal Description 28.3. Functional Description 28.3.1. Initialization 28.3.2. Operation 28.3.2.1. Frame Formats 28.3.2.2. Clock Generation 28.3.2.2.1. The Fractional Baud Rate Generator 28.3.2.3. Data Transmission 28.3.2.3.1. Disabling the Transmitter 28.3.2.4. Data Reception 28.3.2.4.1. Receiver Error Flags 28.3.2.4.2. Disabling the Receiver 28.3.2.4.3. Flushing the Receive Buffer 28.3.3. Communication Modes 28.3.3.1. Synchronous Operation 28.3.3.1.1. Clock Operation 28.3.3.1.2. External Clock Limitations 28.3.3.1.3. USART in Host SPI Mode 28.3.3.1.3.1. Frame Formats 28.3.3.1.3.2. Clock Generation 28.3.3.1.3.3. Data Transmission 28.3.3.1.3.4. Data Reception 28.3.3.1.3.5. USART in Host SPI Mode vs. SPI 28.3.3.2. Asynchronous Operation 28.3.3.2.1. Clock Recovery 28.3.3.2.2. Data Recovery 28.3.3.2.3. Error Tolerance 28.3.3.2.4. Double-Speed Operation 28.3.3.2.5. Auto-Baud 28.3.3.2.6. Half-Duplex Operation 28.3.3.2.6.1. One-Wire Mode 28.3.3.2.6.2. RS-485 Mode 28.3.3.2.7. IRCOM Mode of Operation 28.3.4. Additional Features 28.3.4.1. Parity 28.3.4.2. Start-of-Frame Detection 28.3.4.3. Multiprocessor Communication 28.3.4.3.1. Using Multiprocessor Communication 28.3.5. Events 28.3.6. Interrupts 28.4. Register Summary 28.5. Register Description 28.5.1. Receiver Data Register Low Byte 28.5.2. Receiver Data Register High Byte 28.5.3. Transmit Data Register Low Byte 28.5.4. Transmit Data Register High Byte 28.5.5. USART Status Register 28.5.6. Control A 28.5.7. Control B 28.5.8. Control C - Normal Mode 28.5.9. Control C - Host SPI Mode 28.5.10. Baud Register 28.5.11. Control D 28.5.12. Debug Control Register 28.5.13. IrDA Control Register 28.5.14. IRCOM Transmitter Pulse Length Control Register 28.5.15. IRCOM Receiver Pulse Length Control Register 29. SPI - Serial Peripheral Interface 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Signal Description 29.3. Functional Description 29.3.1. Initialization 29.3.2. Operation 29.3.2.1. Host Mode Operation 29.3.2.1.1. Normal Mode 29.3.2.1.2. Buffer Mode 29.3.2.1.3. SS Pin Functionality in Host Mode - Multi-Host Support 29.3.2.2. Client Mode 29.3.2.2.1. Normal Mode 29.3.2.2.2. Buffer Mode 29.3.2.2.3. SS Pin Functionality in Client Mode 29.3.2.3. Data Modes 29.3.2.4. Events 29.3.2.5. Interrupts 29.4. Register Summary 29.5. Register Description 29.5.1. Control A 29.5.2. Control B 29.5.3. Interrupt Control 29.5.4. Interrupt Flags - Normal Mode 29.5.5. Interrupt Flags - Buffer Mode 29.5.6. Data 30. TWI - Two-Wire Interface 30.1. Features 30.2. Overview 30.2.1. Block Diagram 30.2.2. Signal Description 30.3. Functional Description 30.3.1. General TWI Bus Concepts 30.3.2. TWI Basic Operation 30.3.2.1. Initialization 30.3.2.1.1. Host Initialization 30.3.2.1.2. Client Initialization 30.3.2.2. TWI Host Operation 30.3.2.2.1. Clock Generation 30.3.2.2.2. TWI Bus State Logic 30.3.2.2.3. Transmitting Address Packets 30.3.2.2.3.1. Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’ 30.3.2.2.3.2. Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’ 30.3.2.2.3.3. Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client 30.3.2.2.3.4. Case M4: Arbitration Lost or Bus Error 30.3.2.2.4. Transmitting Data Packets 30.3.2.2.5. Receiving Data Packets 30.3.2.3. TWI Client Operation 30.3.2.3.1. Receiving Address Packets 30.3.2.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set to ‘0’ 30.3.2.3.1.2. Case S2: Address Packet Accepted - Direction Bit Set to ‘1’ 30.3.2.3.1.3. Case S3: Stop Condition Received 30.3.2.3.1.4. Case S4: Collision 30.3.2.3.2. Receiving Data Packets 30.3.2.3.3. Transmitting Data Packets 30.3.3. Additional Features 30.3.3.1. SMBus 30.3.3.1.1. Compliance to SMBus Specifications 30.3.3.2. Multi-Host 30.3.3.3. Smart Mode 30.3.3.4. Dual Mode 30.3.3.5. Quick Command Mode 30.3.3.6. 10-Bit Address 30.3.4. Interrupts 30.3.5. Sleep Mode Operation 30.3.6. Debug Operation 30.4. Register Summary 30.5. Register Description 30.5.1. Control A 30.5.2. Dual Mode Control Configuration 30.5.3. Debug Control 30.5.4. Host Control A 30.5.5. Host Control B 30.5.6. Host Status 30.5.7. Host Baud Rate 30.5.8. Host Address 30.5.9. Host Data 30.5.10. Client Control A 30.5.11. Client Control B 30.5.12. Client Status 30.5.13. Client Address 30.5.14. Client Data 30.5.15. Client Address Mask 31. CRCSCAN - Cyclic Redundancy Check Memory Scan 31.1. Features 31.2. Overview 31.2.1. Block Diagram 31.3. Functional Description 31.3.1. Initialization 31.3.2. Operation 31.3.2.1. Checksum 31.3.3. Interrupts 31.3.4. Sleep Mode Operation 31.3.5. Debug Operation 31.4. Register Summary 31.5. Register Description 31.5.1. Control A 31.5.2. Control B 31.5.3. Status 32. CCL - Configurable Custom Logic 32.1. Features 32.2. Overview 32.2.1. Block Diagram 32.2.2. Signal Description 32.2.2.1. CCL Input Selection MUX 32.3. Functional Description 32.3.1. Operation 32.3.1.1. Enable-Protected Configuration 32.3.1.2. Enabling, Disabling, and Resetting 32.3.1.3. Truth Table Logic 32.3.1.4. Truth Table Inputs Selection 32.3.1.5. Filter 32.3.1.6. Edge Detector 32.3.1.7. Sequencer Logic 32.3.1.8. Clock Source Settings 32.3.2. Interrupts 32.3.3. Events 32.3.4. Sleep Mode Operation 32.4. Register Summary 32.5. Register Description 32.5.1. Control A 32.5.2. Sequencer Control 0 32.5.3. Sequencer Control 1 32.5.4. Interrupt Control 0 32.5.5. Interrupt Flag 32.5.6. LUT n Control A 32.5.7. LUT n Control B 32.5.8. LUT n Control C 32.5.9. TRUTHn 33. AC - Analog Comparator 33.1. Features 33.2. Overview 33.2.1. Block Diagram 33.2.2. Signal Description 33.3. Functional Description 33.3.1. Initialization 33.3.2. Operation 33.3.2.1. Input Hysteresis 33.3.2.2. Input and Reference Selection 33.3.2.3. Normal Mode 33.3.2.4. Power Modes 33.3.2.5. Window Mode 33.3.3. Events 33.3.4. Interrupts 33.3.5. Sleep Mode Operation 33.4. Register Summary 33.5. Register Description 33.5.1. Control A 33.5.2. Control B 33.5.3. MUX Control 33.5.4. DAC Voltage Reference 33.5.5. Interrupt Control 33.5.6. Status 34. ADC - Analog-to-Digital Converter 34.1. Features 34.2. Overview 34.2.1. Block Diagram 34.2.2. Signal Description 34.3. Functional Description 34.3.1. Definitions 34.3.2. Basic Operation 34.3.3. Operation 34.3.3.1. Operation Modes 34.3.3.2. Conversion Triggers 34.3.3.3. Output Formats 34.3.3.4. ADC Clock 34.3.3.5. Input and Reference Selection 34.3.3.5.1. Programmable Gain Amplifier 34.3.3.5.2. Offset Reduction by Sign Chopping 34.3.3.5.3. Analog Input Circuit 34.3.3.6. Conversion Timing 34.3.3.6.1. Single Conversion 34.3.3.6.2. Series Accumulation 34.3.3.6.3. Burst Accumulation 34.3.3.6.4. Single Conversion Mode with PGA 34.3.3.6.5. Series Accumulation with PGA 34.3.3.6.6. Burst Accumulation with PGA 34.3.3.7. Temperature Measurement 34.3.3.8. Window Comparator 34.3.4. Events 34.3.5. Interrupts 34.3.6. Sleep Mode Operation 34.3.7. Debug Operation 34.4. Register Summary 34.5. Register Description 34.5.1. Control A 34.5.2. Control B 34.5.3. Control C 34.5.4. Control D 34.5.5. Interrupt Control 34.5.6. Interrupt Flags 34.5.7. Status 34.5.8. Debug Control 34.5.9. Control E 34.5.10. Control F 34.5.11. Command 34.5.12. PGA Control 34.5.13. Positive Input Multiplexer 34.5.14. Negative Input Multiplexer 34.5.15. Result 34.5.16. Sample 34.5.17. Temporary n 34.5.18. Window Comparator Low Threshold 34.5.19. Window Comparator High Threshold 35. DAC - Digital-to-Analog Converter 35.1. Features 35.2. Overview 35.2.1. Block Diagram 35.2.2. Signal Description 35.3. Functional Description 35.3.1. Initialization 35.3.2. Operation 35.3.2.1. Enabling, Disabling and Resetting 35.3.2.2. Starting a Conversion 35.3.2.3. DAC Output 35.3.2.3.1. Unbuffered Output as Source For Internal Peripherals 35.3.2.3.2. Buffered Output 35.3.3. Sleep Mode Operation 35.4. Register Summary 35.5. Register Description 35.5.1. Control A 35.5.2. DATA 36. UPDI - Unified Program and Debug Interface 36.1. Features 36.2. Overview 36.2.1. Block Diagram 36.2.2. Addressing the Program Memory Space 36.2.3. Clocks 36.2.4. Physical Layer 36.2.5. Pinout Description 36.3. Functional Description 36.3.1. Principle of Operation 36.3.1.1. UPDI UART 36.3.1.2. BREAK Character 36.3.1.2.1. BREAK in One-Wire Mode 36.3.1.3. SYNCH Character 36.3.1.3.1. SYNCH in One-Wire Mode 36.3.2. Operation 36.3.2.1. UPDI Enabling 36.3.2.1.1. One-Wire Enable 36.3.2.1.2. UPDI Enable with High-Voltage Override of UPDI Pin 36.3.2.2. UPDI Disabling 36.3.2.2.1. Disable During Start-Up 36.3.2.2.1.1. Time-Out Disable 36.3.2.2.1.2. Incorrect SYNCH Pattern 36.3.2.2.2. UPDI Regular Disable 36.3.2.3. UPDI Communication Error Handling 36.3.2.4. Direction Change 36.3.3. UPDI Instruction Set 36.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 36.3.3.2. STS - Store Data to Data Space Using Direct Addressing 36.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 36.3.3.4. ST - Store Data from UPDI to Data Space Using Indirect Addressing 36.3.3.5. LDCS - Load Data from Control and Status Register Space 36.3.3.6. STCS - Store Data to Control and Status Register Space 36.3.3.7. REPEAT - Set Instruction Repeat Counter 36.3.3.8. KEY - Set Activation Key or Send System Information Block 36.3.4. CRC Checking of Flash During Boot 36.3.5. System Clock Measurement with UPDI 36.3.6. Inter-Byte Delay 36.3.7. System Information Block 36.3.8. Enabling of Key Protected Interfaces 36.3.8.1. Chip Erase 36.3.8.2. NVM Programming 36.3.8.3. User Row Programming 36.3.9. Events 36.3.10. Sleep Mode Operation 36.4. Register Summary 36.5. Register Description 36.5.1. Status A 36.5.2. Status B 36.5.3. Control A 36.5.4. Control B 36.5.5. ASI Key Status 36.5.6. ASI Reset Request 36.5.7. ASI Control A 36.5.8. ASI System Control A 36.5.9. ASI System Status 36.5.10. ASI CRC Status 37. Instruction Set Summary 38. Electrical Characteristics 38.1. Disclaimer 38.2. Absolute Maximum Ratings 38.3. Standard Operating Conditions 38.4. Supply Voltage 38.5. Power Consumption 38.6. Peripherals Power Consumption 38.7. I/O Pins 38.8. Memory Programming Specifications 38.9. Thermal Specifications 38.10. CLKCTRL 38.10.1. Internal Oscillators 38.10.2. XOSC32K 38.10.3. XOSCHF 38.10.4. External Clock 38.10.5. System Clock 38.11. RSTCTRL and BOD 38.12. VREF 38.13. USART 38.14. SPI 38.15. TWI 38.16. DAC 38.17. ADC 38.18. AC 38.19. UPDI 39. Characteristics Graphs 40. Ordering Information 41. Package Drawings 41.1. Online Package Drawings 41.2. Package Marking Information 41.2.1. 28-Pin SPDIP 41.2.2. 28-Pin SSOP 41.2.3. 28-Pin VQFN 41.2.4. 32-Pin TQFP 41.2.5. 32-Pin VQFN 41.2.6. 32-Pin VQFN Wettable Flanks 41.2.7. 48-Pin TQFP 41.2.8. 48-Pin VQFN 41.2.9. 48-Pin VQFN Wettable Flanks 41.3. 28-Pin SPDIP 41.4. 28-Pin SSOP 41.5. 28-Pin VQFN 41.6. 28-Pin VQFN Wettable Flanks 41.7. 32-Pin TQFP 41.8. 32-Pin VQFN 41.9. 32-Pin VQFN Wettable Flanks 41.10. 48-Pin TQFP 41.11. 48-Pin VQFN 41.12. 48-Pin VQFN Wettable Flanks 42. Data Sheet Revision History 42.1. Rev. A - 09/2022 43. Microchip Information The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service