SPI Timing Characteristics

The SPI timing is provided in the following figure and table.

Figure 1. SPI Timing Diagram (SPI Mode CPOL = 0, CPHA = 0)
Table 1. SPI Client Timing Parameters(1)
Parameter Symbol Min. Max. Units
Clock Input Frequency(2) fSCK 48 MHz
Clock Low Pulse Width tWL 4 ns
Clock High Pulse Width tWH 5
Clock Rise Time tLH 0 7
Clock Fall Time tHL 0 7
TXD Output Delay(3) tODLY 4 9 from SCK fall
RXD Input Setup Time tISU 1
RXD Input Hold Time tIHD 5
SSN Input Setup Time tSUSSN 3
SSN Input Hold Time tHDSSN 5.5
Notes:
  1. 1.Timing is applicable to all SPI modes.
  2. 2.Maximum clock frequency specified is limited by the SPI Client interface internal design, actual maximum clock frequency can be lower and depends on the specific PCB layout.
  3. 3.Timing based on 15 pF output loading under all conditions, tLH + tWH + tHL + tWL must be less than or equal to 1/ fSCK.