The SPI timing is provided in the following figure and table.
Parameter | Symbol | Min. | Max. | Units |
---|---|---|---|---|
Clock Input Frequency(2) | fSCK | — | 48 | MHz |
Clock Low Pulse Width | tWL | 4 | — | ns |
Clock High Pulse Width | tWH | 5 | — | |
Clock Rise Time | tLH | 0 | 7 | |
Clock Fall Time | tHL | 0 | 7 | |
TXD Output Delay(3) | tODLY | 4 | 9 from SCK fall | |
RXD Input Setup Time | tISU | 1 | — | |
RXD Input Hold Time | tIHD | 5 | — | |
SSN Input Setup Time | tSUSSN | 3 | — | |
SSN Input Hold Time | tHDSSN | 5.5 | — |