Program/Verify Commands

Once a device has entered the ICSP Program/Verify mode (using either high-voltage or LVP entry), the programming host device may issue six commands to the microcontroller, each eight bits in length. The commands are summarized in Table 1 and are used to erase or program the device based on the location of the Program Counter (PC).

Some 8-bit commands also have an associated data payload (such as Load PC Address and Read Data from NVM).

If the host device issues an 8-bit command byte that has an associated data payload, the host device is responsible for sending additional 24 clock pulses (e.g., three 8-bit bytes) to send or receive the payload data associated with the command.

The payload field size is compatible with many 8-bit SPI-based systems. Within each 24-bit payload field, the first bit transmitted is always a Start bit, followed by a variable number of Pad bits, then by the useful data payload bits and ending with one Stop bit. The useful data payload bits are always transmitted MSb first.

When the programming device issues a command that involves a host to the microcontroller payload (e.g., Load PC Address), the Start, Stop and Pad bits will all be driven by the programmer to ‘0’. When the programming host device issues a command that involves the microcontroller to host payload data (e.g., Read Data from NVM), the Start, Stop and Pad bits will be treated as ‘don't care’ bits and the values will be ignored by the host.

When the programming host device issues an 8-bit command byte to the microcontroller, the host will wait a specified minimum amount of delay (which is command-specific) prior to sending any additional clock pulses (associated with either a 24-bit data payload field or the next command byte).

Table 1. ICSP™ Command Set Summary(1)
Command Name Command Value Payload Expected Delay after Command Data/Note
Binary (MSb … LSb) Hex
Load PC Address 1000 0000 80 Yes TDLY Payload value = PC
Bulk Erase 0001 1000 18 Yes TERAB The payload carries the information of the regions that need to be bulk erased
Page Erase Program Memory 1111 0000 F0 No TERAS The page addressed by the MSbs of the PC is erased; LSbs are ignored
Read Data from NVM 1111 11J0 FC/FE Yes TDLY Data output ‘0’ if code-protect is enabled:

J = 0: PC is unchanged;

J = 1: PC = PC + n(2) after reading

Increment Address 1111 1000 F8 No TDLY PC = PC + n(2)
Program Data 11J0 0000 C0/E0 Yes TPROG Payload value = Data Word;

J = 0: PC is unchanged;

J = 1: PC = PC + n after writing

  1. 1.All the clock pulses for both the 8-bit commands and the 24-bit payload fields are generated by the host programming device. The microcontroller does not drive the ICSPCLK line. The ICSPDAT signal is a bidirectional data line. For all commands and payload fields, except the Read Data from NVM payload, the host programming device continuously drives the ICSPDAT line. Both the host programmer device and the microcontroller will latch received ICSPDAT values on the falling edge of the ICSPCLK line. When the microcontroller receives ICSPDAT line values from the host programmer, the ICSPDAT values must be valid a minimum of TDS before the falling edges of ICSPCLK and will remain valid for a minimum of TDH after the falling edge of ICSPDAT. See Figure 1.
  2. 2.PC is incremented by n = 1 for data memory and Configuration Bytes, and n = 2 for all other regions.
Figure 1. Clock and Data Timing