Pin Change Interrupt Control Register

Name:
PCICR
Offset:
0x12
Reset:
0x00
Access:
-
Bit76543210
PCIE0
AccessR/W
Reset0

Bit 0 – PCIE0: Pin Change Interrupt Enable 0

Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK Register.