USART Control and Status Register 0 C

Name:
UCSR0C
Offset:
0x0C
Reset:
0x06
Access:
-
Bit76543210
UMSEL0n[1:0]UPM0n[1:0]USBS0UCSZ01 / UDORD0UCSZ00 / UCPHA0UCPOL0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000110

Bits 7:6 – UMSEL0n: USART Mode Select 0 n [n = 1:0]

USART Mode Select 0 n [n = 1:0]

These bits select the mode of operation of the USART0

Table 1. USART Mode Selection
UMSEL0[1:0] Mode
00 Asynchronous USART
01 Synchronous USART
10 Reserved
11 Master SPI (MSPIM)(1)
Note:
  1. 1.The UDORD0, UCPHA0, and UCPOL0 can be set in the same write operation where the MSPIM is enabled.

Bits 5:4 – UPM0n: USART Parity Mode 0 n [n = 1:0]

USART Parity Mode 0 n [n = 1:0]

These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the UPE0 Flag in UCSR0A will be set.

Table 2. USART Mode Selection
UPM0[1:0] ParityMode
00 Disabled
01 Reserved
10 Enabled, Even Parity
11 Enabled, Odd Parity

These bits are reserved in Master SPI Mode (MSPIM).

Bit 3 – USBS0: USART Stop Bit Select 0

USART Stop Bit Select 0

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.

Table 3. Stop Bit Settings
USBS0 Stop Bit(s)
0 1-bit
1 2-bit

This bit is reserved in Master SPI Mode (MSPIM).

Bit 2 – UCSZ01 / UDORD0: USART Character Size / Data Order

USART Character Size / Data Order

UCSZ0[1:0]: USART Modes: The UCSZ0[1:0] bits combined with the UCSZ02 bit in UCSR0B sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use.

Table 4. Character Size Settings
UCSZ0[2:0] Character Size
000 5-bit
001 6-bit
010 7-bit
011 8-bit
100 Reserved
101 Reserved
110 Reserved
111 9-bit

UDPRD0: Master SPI Mode: When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the USART in SPI Mode - Frame Formats for details.

Bit 1 – UCSZ00 / UCPHA0: USART Character Size / Clock Phase

USART Character Size / Clock Phase

UCSZ00: USART Modes: Refer to UCSZ01.

UCPHA0: Master SPI Mode: The UCPHA0 bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCK0. Refer to the SPI Data Modes and Timing for details.

Bit 0 – UCPOL0: Clock Polarity 0

Clock Polarity 0

USART0 Modes: This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL0 bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK0).

Table 5. USART Clock Polarity Settings
UCPOL0 Transmitted Data Changed (Output of TxD0 Pin) Received Data Sampled (Input on RxD0 Pin)
0 Rising XCK0 Edge Falling XCK0 Edge
1 Falling XCK0 Edge Rising XCK0 Edge

Master SPI Mode: The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0 and UCPHA0 bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing for details.