The EEPROM array in the
AT24CSW04X/AT24CSW08X will be protected
from writing in accordance with the WPB1 and WPB0 bit values as long as the WPRE bit is
set to logic ‘
1’. If the WPRE bit is set to logic ‘
0’,
no portion of the EEPROM array will be protected. The combination of these three bits
creates five possible levels of protection for the device. The protected address ranges
of the memory are shown in
Table 1.
Table 1. Word Address Byte Requirements
for Accessing the Write Protection Register
| Protection
Level |
WPRE |
WPB1 |
WPB0 |
Protected Address Range |
Unprotected Address Range |
| 4-Kbit |
8-Kbit |
4-Kbit |
8-Kbit |
| None |
0 |
X |
X |
None |
None |
000h‑1FFh |
000h‑3FFh |
| Upper ¼ |
1 |
0 |
0 |
180h‑1FFh |
300h‑3FFh |
000h‑17Fh |
000h‑2FFh |
| Upper ½ |
1 |
0 |
1 |
100h‑1FFh |
200h‑3FFh |
000h‑0FFh |
000h‑1FFh |
| Upper ¾ |
1 |
1 |
0 |
080h‑1FFh |
100h‑3FFh |
000h‑07Fh |
000h‑0FFh |
| Full Array |
1 |
1 |
1 |
000h‑1FFh |
000h‑3FFh |
None |
None |