The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the VCC is maintained to the part. The address rollover during a read is from the last byte of the last page to the first byte of the first page of the memory.
A current address read operation will output data according to the
location of the internal data word address counter. This is initiated with a Start
condition, followed by a valid device address byte with the
R/W bit set to logic ‘1’. The device will ACK
this sequence and the current address data word is serially clocked out on the SDA line.
All types of read operations will be terminated if the bus master does not respond with an
ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may send a
Stop condition to complete the protocol, or it can send a Start condition to begin the next
sequence.
- 1. For the AT24CSW04X, the @ indicates the A1 Hardware Address bit which is managed by the ordering code of the device (see Table 3). For the AT24CSW08X, the @ indicates the A9 address bit.
- 2. # indicates the hardware address value which is managed by the ordering code of the device (see Table 3 and Table 4).