Sequential reads are initiated by either a current address read or a random read. After the bus master receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the word address and serially clock out sequential data words. When the maximum memory address is reached, the data word address will rollover and the sequential read will continue from the beginning of the memory array. All types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol or it can send a Start condition to begin the next sequence.
- 1. For the AT24CSW04X, the @ indicates the A1 Hardware Address bit which is managed by the ordering code of the device (see Table 3). For the AT24CSW08X, the @ indicates the A9 address bit.
- 2. # indicates the hardware address value which is managed by the ordering code of the device (see Table 3 and Table 4).