Each global and row global buffer has a gating option for glitch-free enabling and disabling of the clock. The clock-gating enable port driven from the fabric logic can be changed, dynamically. The clock gating feature is accessible by instantiating a clock buffer macro (GCLKINT or RGCLKINT) in the design. The GCLKINT macro provides clock gating at the global buffer level and the RGCLKINT macro provides clock gating at the row global buffer level. The following figure shows a schematic of the clock-gating circuit.
Clock gating is achieved using a latch and enable (EN) that is driven by the user logic implemented in the FPGA fabric. The latch is transparent when the clock input is in low phase. The latch is in a Hold state when the clock is in high phase. The AND gate at the output allows enabling or disabling of the clock based on the latch output. The clock is active when the EN signal is HIGH, and it is gated off and driven LOW when the EN signal is LOW.
The following figure shows the timing waveforms for buffers with clock gating enabled. See respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet for the minimum setup and hold time for the clock gating enable signal.
For falling-edge clocks, EN signal must arrive by prior rising edge (earlier than usual). Unused global resources such as: RGBs and GBs are tied-off automatically to reduce the dynamic power consumption.