Contents
Introduction
AVR® DB Family Overview
2.1. Memory Overview
2.2. Peripheral Overview
Features
4. Block Diagram
5. Pinout
5.1. 28-pin SSOP, SOIC and SPDIP
5.2. 32-pin VQFN and TQFP
5.3. 48-pin VQFN and TQFP
5.4. 64-pin VQFN and TQFP
6. I/O Multiplexing and Considerations
6.1. I/O Multiplexing
7. Hardware Guidelines
7.1. General Guidelines
7.1.1. Special Consideration for Packages with Center Pad
7.2. Connection for Power Supply
7.2.1. Digital Power Supply
7.2.2. Analog Power Supply
7.2.3. Multi-Voltage I/O
7.3. Connection for RESET
7.4. Connection for UPDI Programming
7.5. Connecting External Crystal Oscillators
7.5.1. Connection for XTAL32K (External 32.768 kHz Crystal Oscillator)
7.5.2. Connection for XTALHF (External HF Crystal Oscillator)
7.6. Connection for External Voltage Reference
8. Power Supply
8.1. Power Domains
8.2. Voltage Regulator
8.3. Power-Up
9. Conventions
9.1. Numerical Notation
9.2. Memory Size and Type
9.3. Frequency and Time
9.4. Registers and Bits
9.4.1. Addressing Registers from Header Files
9.5. ADC Parameter Definitions
10. AVR CPU
10.1. Features
10.2. Overview
10.3. Architecture
10.3.1. Arithmetic Logic Unit (ALU)
10.3.1.1. Hardware Multiplier
10.4. Functional Description
10.4.1. Program Flow
10.4.2. Instruction Execution Timing
10.4.3. Status Register
10.4.4. Stack and Stack Pointer
10.4.5. Register File
10.4.5.1. The X-, Y-, and Z-Registers
10.4.6. Configuration Change Protection (CCP)
10.4.6.1. Sequence for Write Operation to Configuration Change Protected I/O Registers
10.4.6.2. Sequence for Execution of Self-Programming
10.4.7. On-Chip Debug Capabilities
10.5. Register Summary
10.6. Register Description
10.6.1. CCP
10.6.2. SP
10.6.3. SREG
11. Memories
11.1. Overview
11.2. Memory Map
11.3. In-System Reprogrammable Flash Program Memory
11.4. SRAM Data Memory
11.5. EEPROM Data Memory
11.6. SIGROW - Signature Row
11.6.1. Signature Row Summary
11.6.2. Signature Row Description
11.6.2.1. Device ID n
11.6.2.2. Temperature Sensor Calibration n
11.6.2.3. Serial Number Byte n
11.7. USERROW - User Row
11.8. FUSE - Configuration and User Fuses
11.8.1. Fuse Summary
11.8.2. Fuse Description
11.8.2.1. Watchdog Timer Configuration
11.8.2.2. Brown-Out Detector Configuration
11.8.2.3. Oscillator Configuration
11.8.2.4. System Configuration 0
11.8.2.5. System Configuration 1
11.8.2.6. Code Size
11.8.2.7. Boot Size
11.9. LOCK - Memory Sections Access Protection
11.9.1. Lock Summary
11.9.2. Lock Description
11.9.2.1. Lock Key
11.10. I/O Memory
11.10.1. Single-Cycle I/O Registers
11.10.2. Extended I/O Registers
11.10.3. Accessing 16-bit Registers
11.10.4. Accessing 24-bit Registers
12. GPR - General Purpose Registers
12.1. Register Summary
12.2. Register Description
12.2.1. General Purpose Register n
13. Peripherals and Architecture
13.1. Peripheral Address Map
13.2. Interrupt Vector Mapping
13.3. SYSCFG - System Configuration
13.3.1. Register Summary
13.3.2. Register Description
13.3.2.1. Device Revision ID Register
14. NVMCTRL - Nonvolatile Memory Controller
14.1. Features
14.2. Overview
14.2.1. Block Diagram
14.3. Functional Description
14.3.1. Memory Organization
14.3.1.1. Flash
14.3.1.2. EEPROM
14.3.1.3. Signature Row
14.3.1.4. User Row
14.3.1.5. Fuses
14.3.2. Memory Access
14.3.2.1. Read
14.3.2.2. Programming
14.3.2.3. Command Modes
14.3.2.3.1. Flash Write Mode
14.3.2.3.2. Flash Page Erase Mode
14.3.2.3.3. Flash Multi-Page Erase Mode
14.3.2.3.4. EEPROM Write Mode
14.3.2.3.5. EEPROM Erase/Write Mode
14.3.2.3.6. EEPROM Byte Erase Mode
14.3.2.3.7. EEPROM Multi-Byte Erase Mode
14.3.2.3.8. Chip Erase Command
14.3.2.3.9. EEPROM Erase Command
14.3.3. Preventing Flash/EEPROM Corruption
14.3.4. Interrupts
14.3.5. Sleep Mode Operation
14.3.6. Configuration Change Protection
14.4. Register Summary
14.5. Register Description
14.5.1. Control A
14.5.2. Control B
14.5.3. Status
14.5.4. Interrupt Control
14.5.5. Interrupt Flags
14.5.6. Data
14.5.7. Address
15. CLKCTRL - Clock Controller
15.1. Features
15.2. Overview
15.2.1. Block Diagram - CLKCTRL
15.2.2. Signal Description
15.3. Functional Description
15.3.1. Initialization
15.3.2. Main Clock Selection and Prescaler
15.3.3. Main Clock After Reset
15.3.4. Clock Sources
15.3.4.1. Internal Oscillators
15.3.4.1.1. Internal High-Frequency Oscillator (OSCHF)
15.3.4.1.2. 32.768 kHz Oscillator (OSC32K)
15.3.4.2. External Clock Sources
15.3.4.2.1. High-Frequency Crystal Oscillator (XOSCHF)
15.3.4.2.2. 32.768 kHz Crystal Oscillator (XOSC32K)
15.3.5. Phase-Locked Loop (PLL)
15.3.6. Manual Tuning and Auto-Tune
15.3.7. Clock Failure Detection (CFD)
15.3.7.1. CFD Operation
15.3.7.2. Condition Clearing
15.3.7.3. CFD Test
15.3.7.3.1. Testing the CFD Without Influencing the Main Clock
15.3.7.3.2. Testing the CFD and Changing the Main Clock to the Start-up Clock Source
15.3.8. Sleep Mode Operation
15.3.9. Configuration Change Protection
15.4. Register Summary
15.5. Register Description
15.5.1. Main Clock Control A
15.5.2. Main Clock Control B
15.5.3. Main Clock Control C
15.5.4. Main Clock Interrupt Control
15.5.5. Main Clock Interrupt Flags
15.5.6. Main Clock Status
15.5.7. Internal High-Frequency Oscillator Control A
15.5.8. Internal High-Frequency Oscillator Frequency Tune
15.5.9. PLL Control A
15.5.10. 32.768 kHz Oscillator Control A
15.5.11. 32.768 kHz Crystal Oscillator Control A
15.5.12. External High-Frequency Oscillator Control A
16. SLPCTRL - Sleep Controller
16.1. Features
16.2. Overview
16.2.1. Block Diagram
16.3. Functional Description
16.3.1. Initialization
16.3.2. Voltage Regulator Configuration
16.3.3. Operation
16.3.3.1. Sleep Modes
16.3.3.2. Wake-up Time
16.3.4. Debug Operation
16.3.5. Configuration Change Protection
16.4. Register Summary
16.5. Register Description
16.5.1. Control A
16.5.2. Voltage Regulator Control Register
17. RSTCTRL - Reset Controller
17.1. Features
17.2. Overview
17.2.1. Block Diagram
17.2.2. Signal Description
17.3. Functional Description
17.3.1. Initialization
17.3.2. Operation
17.3.2.1. Reset Sources
17.3.2.1.1. Power-on Reset (POR)
17.3.2.1.2. Brown-out Detector (BOD) Reset
17.3.2.1.3. External Reset (RESET)
17.3.2.1.4. Watchdog Timer (WDT) Reset
17.3.2.1.5. Software Reset (SWRST)
17.3.2.1.6. Unified Program and Debug Interface (UPDI) Reset
17.3.2.1.7. Domains Affected By Reset
17.3.2.2. Reset Time
17.3.3. Sleep Mode Operation
17.3.4. Configuration Change Protection
17.4. Register Summary
17.5. Register Description
17.5.1. Reset Flag Register
17.5.2. Software Reset Register
18. CPUINT - CPU Interrupt Controller
18.1. Features
18.2. Overview
18.2.1. Block Diagram
18.3. Functional Description
18.3.1. Initialization
18.3.2. Operation
18.3.2.1. Enabling, Disabling and Resetting
18.3.2.2. Interrupt Vector Locations
18.3.2.3. Interrupt Response Time
18.3.2.4. Interrupt Priority
18.3.2.4.1. Non-Maskable Interrupts
18.3.2.4.2. High-Priority Interrupt
18.3.2.4.3. Normal-Priority Interrupts
18.3.2.4.3.1. Static Scheduling
18.3.2.4.3.2. Modified Static Scheduling
18.3.2.4.3.3. Round Robin Scheduling
18.3.2.5. Compact Vector Table
18.3.3. Debug Operation
18.3.4. Configuration Change Protection
18.4. Register Summary
18.5. Register Description
18.5.1. Control A
18.5.2. Status
18.5.3. Interrupt Priority Level 0
18.5.4. Interrupt Vector with Priority Level 1
19. EVSYS - Event System
19.1. Features
19.2. Overview
19.2.1. Block Diagram
19.2.2. Signal Description
19.3. Functional Description
19.3.1. Initialization
19.3.2. Operation
19.3.2.1. Event User Multiplexer Setup
19.3.2.2. Event System Channel
19.3.2.3. Event Generators
19.3.2.4. Event Users
19.3.2.5. Synchronization
19.3.2.6. Software Event
19.3.3. Sleep Mode Operation
19.3.4. Debug Operation
19.4. Register Summary
19.5. Register Description
19.5.1. Software Events
19.5.2. Channel n Generator Selection
19.5.3. User Channel MUX
20. PORTMUX - Port Multiplexer
20.1. Overview
20.2. Register Summary
20.3. Register Description
20.3.1. EVSYS Pin Position
20.3.2. CCL LUTn Pin Position
20.3.3. USARTn Pin Position
20.3.4. USARTn Pin Position
20.3.5. SPIn Pin Position
20.3.6. TWIn Pin Position
20.3.7. TCAn Pin Position
20.3.8. TCBn Pin Position
20.3.9. TCDn Pin Position
20.3.10. ACn Pin Position
20.3.11. ZCDn Pin Position
21. PORT - I/O Pin Configuration
21.1. Features
21.2. Overview
21.2.1. Block Diagram
21.2.2. Signal Description
21.3. Functional Description
21.3.1. Initialization
21.3.2. Operation
21.3.2.1. Basic Functions
21.3.2.2. Port Configuration
21.3.2.3. Pin Configuration
21.3.2.4. Multi-Pin Configuration
21.3.2.5. Virtual Ports
21.3.2.6. Peripheral Override
21.3.2.7. Multi-Voltage I/O
21.3.3. Interrupts
21.3.3.1. Asynchronous Sensing Pin Properties
21.3.4. Events
21.3.5. Sleep Mode Operation
21.3.6. Debug Operation
21.4. Register Summary - PORTx
21.5. Register Description - PORTx
21.5.1. Data Direction
21.5.2. Data Direction Set
21.5.3. Data Direction Clear
21.5.4. Data Direction Toggle
21.5.5. Output Value
21.5.6. Output Value Set
21.5.7. Output Value Clear
21.5.8. Output Value Toggle
21.5.9. Input Value
21.5.10. Interrupt Flags
21.5.11. Port Control
21.5.12. Multi-Pin Configuration
21.5.13. Multi-Pin Control Update Mask
21.5.14. Multi-Pin Control Set Mask
21.5.15. Multi-Pin Control Clear Mask
21.5.16. Pin n Control
21.6. Register Summary - VPORTx
21.7. Register Description - VPORTx
21.7.1. Data Direction
21.7.2. Output Value
21.7.3. Input Value
21.7.4. Interrupt Flags
22. MVIO - Multi-Voltage I/O
22.1. Features
22.2. Overview
22.2.1. Block Diagram
22.2.2. Signal Description
22.3. Functional Description
22.3.1. Initialization
22.3.2. Operation
22.3.2.1. Power Sequencing
22.3.2.2. Voltage Measurement
22.3.3. Events
22.3.4. Interrupts
22.3.5. Sleep Mode Operation
22.3.6. Debug Operation
22.4. Register Summary
22.5. Register Description
22.5.1. Interrupt Control
22.5.2. Interrupt Flags
22.5.3. Status
23. BOD - Brown-out Detector
23.1. Features
23.2. Overview
23.2.1. Block Diagram
23.3. Functional Description
23.3.1. Initialization
23.3.2. Interrupts
23.3.3. Sleep Mode Operation
23.3.4. Configuration Change Protection
23.4. Register Summary
23.5. Register Description
23.5.1. Control A
23.5.2. Control B
23.5.3. VLM Control
23.5.4. Interrupt Control
23.5.5. VLM Interrupt Flags
23.5.6. VLM Status
24. VREF - Voltage Reference
24.1. Features
24.2. Overview
24.2.1. Block Diagram
24.3. Functional Description
24.3.1. Initialization
24.4. Register Summary
24.5. Register Description
24.5.1. ADC0 Reference
24.5.2. DAC0 Reference
24.5.3. Analog Comparator Reference
25. WDT - Watchdog Timer
25.1. Features
25.2. Overview
25.2.1. Block Diagram
25.3. Functional Description
25.3.1. Initialization
25.3.2. Clocks
25.3.3. Operation
25.3.3.1. Normal Mode
25.3.3.2. Window Mode
25.3.3.3. Preventing Unintentional Changes
25.3.4. Sleep Mode Operation
25.3.5. Debug Operation
25.3.6. Synchronization
25.3.7. Configuration Change Protection
25.4. Register Summary
25.5. Register Description
25.5.1. Control A
25.5.2. Status
26. TCA - 16-bit Timer/Counter Type A
26.1. Features
26.2. Overview
26.2.1. Block Diagram
26.2.2. Signal Description
26.3. Functional Description
26.3.1. Definitions
26.3.2. Initialization
26.3.3. Operation
26.3.3.1. Normal Operation
26.3.3.2. Double Buffering
26.3.3.3. Changing the Period
26.3.3.4. Compare Channel
26.3.3.4.1. Waveform Generation
26.3.3.4.2. Frequency (FRQ) Waveform Generation
26.3.3.4.3. Single-Slope PWM Generation
26.3.3.4.4. Dual-Slope PWM
26.3.3.4.5. Port Override for Waveform Generation
26.3.3.5. Timer/Counter Commands
26.3.3.6. Split Mode - Two 8-Bit Timer/Counters
26.3.4. Events
26.3.5. Interrupts
26.3.6. Sleep Mode Operation
26.4. Register Summary - Normal Mode
26.5. Register Description - Normal Mode
26.5.1. Control A - Normal Mode
26.5.2. Control B - Normal Mode
26.5.3. Control C - Normal Mode
26.5.4. Control D - Normal Mode
26.5.5. Control Register E Clear - Normal Mode
26.5.6. Control Register E Set - Normal Mode
26.5.7. Control Register F Clear
26.5.8. Control Register F Set
26.5.9. Event Control
26.5.10. Interrupt Control Register - Normal Mode
26.5.11. Interrupt Flag Register - Normal Mode
26.5.12. Debug Control Register - Normal Mode
26.5.13. Temporary Bits for 16-Bit Access
26.5.14. Counter Register - Normal Mode
26.5.15. Period Register - Normal Mode
26.5.16. Compare n Register - Normal Mode
26.5.17. Period Buffer Register
26.5.18. Compare n Buffer Register
26.6. Register Summary - Split Mode
26.7. Register Description - Split Mode
26.7.1. Control A - Split Mode
26.7.2. Control B - Split Mode
26.7.3. Control C - Split Mode
26.7.4. Control D - Split Mode
26.7.5. Control Register E Clear - Split Mode
26.7.6. Control Register E Set - Split Mode
26.7.7. Interrupt Control Register - Split Mode
26.7.8. Interrupt Flag Register - Split Mode
26.7.9. Debug Control Register - Split Mode
26.7.10. Low Byte Timer Counter Register - Split Mode
26.7.11. High Byte Timer Counter Register - Split Mode
26.7.12. Low Byte Timer Period Register - Split Mode
26.7.13. High Byte Period Register - Split Mode
26.7.14. Compare Register n For Low Byte Timer - Split Mode
26.7.15. High Byte Compare Register n - Split Mode
27. TCB - 16-Bit Timer/Counter Type B
27.1. Features
27.2. Overview
27.2.1. Block Diagram
27.2.2. Signal Description
27.3. Functional Description
27.3.1. Definitions
27.3.2. Initialization
27.3.3. Operation
27.3.3.1. Modes
27.3.3.1.1. Periodic Interrupt Mode
27.3.3.1.2. Time-Out Check Mode
27.3.3.1.3. Input Capture on Event Mode
27.3.3.1.4. Input Capture Frequency Measurement Mode
27.3.3.1.5. Input Capture Pulse-Width Measurement Mode
27.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode
27.3.3.1.7. Single-Shot Mode
27.3.3.1.8. 8-Bit PWM Mode
27.3.3.2. Output
27.3.3.3. 32-Bit Input Capture
27.3.3.4. Noise Canceler
27.3.3.5. Synchronized with Timer/Counter Type A
27.3.4. Events
27.3.5. Interrupts
27.3.6. Sleep Mode Operation
27.4. Register Summary
27.5. Register Description
27.5.1. Control A
27.5.2. Control B
27.5.3. Event Control
27.5.4. Interrupt Control
27.5.5. Interrupt Flags
27.5.6. Status
27.5.7. Debug Control
27.5.8. Temporary Value
27.5.9. Count
27.5.10. Capture/Compare
28. TCD - 12-Bit Timer/Counter Type D
28.1. Features
28.2. Overview
28.2.1. Block Diagram
28.2.2. Signal Description
28.3. Functional Description
28.3.1. Definitions
28.3.2. Initialization
28.3.3. Operation
28.3.3.1. Register Synchronization Categories
28.3.3.2. Waveform Generation Modes
28.3.3.2.1. One Ramp Mode
28.3.3.2.2. Two Ramp Mode
28.3.3.2.3. Four Ramp Mode
28.3.3.2.4. Dual Slope Mode
28.3.3.3. Disabling TCD
28.3.3.4. TCD Inputs
28.3.3.4.1. Input Blanking
28.3.3.4.2. Digital Filter
28.3.3.4.3. Asynchronous Event Detection
28.3.3.4.4. Software Commands
28.3.3.4.5. Input Modes
28.3.3.4.5.1. Input Modes Validity
28.3.3.4.5.2. Input Mode 0: Input Has No Action
28.3.3.4.5.3. Input Mode 1: Stop Output, Jump to the Opposite Compare Cycle, and Wait
28.3.3.4.5.4. Input Mode 2: Stop Output, Execute Opposite Compare Cycle, and Wait
28.3.3.4.5.5. Input Mode 3: Stop Output, Execute Opposite Compare Cycle while Fault Active
28.3.3.4.5.6. Input Mode 4: Stop all Outputs, Maintain Frequency
28.3.3.4.5.7. Input Mode 5: Stop all Outputs, Execute Dead-Time while Fault Active
28.3.3.4.5.8. Input Mode 6: Stop All Outputs, Jump to Next Compare Cycle, and Wait
28.3.3.4.5.9. Input Mode 7: Stop all Outputs, Wait for Software Action
28.3.3.4.5.10. Input Mode 8: Stop Output on Edge, Jump to Next Compare Cycle
28.3.3.4.5.11. Input Mode 9: Stop Output on Edge, Maintain Frequency
28.3.3.4.5.12. Input Mode 10: Stop Output at Level, Maintain Frequency
28.3.3.4.5.13. Input Mode Summary
28.3.3.5. Dithering
28.3.3.6. TCD Counter Capture
28.3.3.7. Output Control
28.3.4. Events
28.3.4.1. Programmable Output Events
28.3.5. Interrupts
28.3.6. Sleep Mode Operation
28.3.7. Debug Operation
28.3.8. Configuration Change Protection
28.4. Register Summary
28.5. Register Description
28.5.1. Control A
28.5.2. Control B
28.5.3. Control C
28.5.4. Control D
28.5.5. Control E
28.5.6. Event Control A
28.5.7. Event Control B
28.5.8. Interrupt Control
28.5.9. Interrupt Flags
28.5.10. Status
28.5.11. Input Control A
28.5.12. Input Control B
28.5.13. Fault Control
28.5.14. Delay Control
28.5.15. Delay Value
28.5.16. Dither Control
28.5.17. Dither Value
28.5.18. Debug Control
28.5.19. Capture A
28.5.20. Capture B
28.5.21. Compare Set A
28.5.22. Compare Set B
28.5.23. Compare Clear A
28.5.24. Compare Clear B
29. RTC - Real-Time Counter
29.1. Features
29.2. Overview
29.2.1. Block Diagram
29.3. Clocks
29.4. RTC Functional Description
29.4.1. Initialization
29.4.1.1. Configure the Clock CLK_RTC
29.4.1.2. Configure RTC
29.4.2. Operation - RTC
29.4.2.1. Enabling and Disabling
29.5. PIT Functional Description
29.5.1. Initialization
29.5.2. Operation - PIT
29.5.2.1. Enabling and Disabling
29.5.2.2. PIT Interrupt Timing
29.6. Crystal Error Correction
29.7. Events
29.8. Interrupts
29.9. Sleep Mode Operation
29.10. Synchronization
29.11. Debug Operation
29.12. Register Summary
29.13. Register Description
29.13.1. Control A
29.13.2. Status
29.13.3. Interrupt Control
29.13.4. Interrupt Flag
29.13.5. Temporary
29.13.6. Debug Control
29.13.7. Crystal Frequency Calibration
29.13.8. Clock Selection
29.13.9. Count
29.13.10. Period
29.13.11. Compare
29.13.12. Periodic Interrupt Timer Control A
29.13.13. Periodic Interrupt Timer Status
29.13.14. PIT Interrupt Control
29.13.15. PIT Interrupt Flag
29.13.16. Periodic Interrupt Timer Debug Control
30. USART - Universal Synchronous and Asynchronous Receiver and Transmitter
30.1. Features
30.2. Overview
30.2.1. Block Diagram
30.2.2. Signal Description
30.3. Functional Description
30.3.1. Initialization
30.3.2. Operation
30.3.2.1. Frame Formats
30.3.2.2. Clock Generation
30.3.2.2.1. The Fractional Baud Rate Generator
30.3.2.3. Data Transmission
30.3.2.3.1. Disabling the Transmitter
30.3.2.4. Data Reception
30.3.2.4.1. Receiver Error Flags
30.3.2.4.2. Disabling the Receiver
30.3.2.4.3. Flushing the Receive Buffer
30.3.3. Communication Modes
30.3.3.1. Synchronous Operation
30.3.3.1.1. Clock Operation
30.3.3.1.2. External Clock Limitations
30.3.3.1.3. USART in Host SPI Mode
30.3.3.1.3.1. Frame Formats
30.3.3.1.3.2. Clock Generation
30.3.3.1.3.3. Data Transmission
30.3.3.1.3.4. Data Reception
30.3.3.1.3.5. USART in Host SPI Mode vs. SPI
30.3.3.2. Asynchronous Operation
30.3.3.2.1. Clock Recovery
30.3.3.2.2. Data Recovery
30.3.3.2.3. Error Tolerance
30.3.3.2.4. Double-Speed Operation
30.3.3.2.5. Auto-Baud
30.3.3.2.6. Half-Duplex Operation
30.3.3.2.6.1. One-Wire Mode
30.3.3.2.6.2. RS-485 Mode
30.3.3.2.7. IRCOM Mode of Operation
30.3.4. Additional Features
30.3.4.1. Parity
30.3.4.2. Start-of-Frame Detection
30.3.4.3. Multiprocessor Communication
30.3.4.3.1. Using Multiprocessor Communication
30.3.5. Events
30.3.6. Interrupts
30.4. Register Summary
30.5. Register Description
30.5.1. Receiver Data Register Low Byte
30.5.2. Receiver Data Register High Byte
30.5.3. Transmit Data Register Low Byte
30.5.4. Transmit Data Register High Byte
30.5.5. USART Status Register
30.5.6. Control A
30.5.7. Control B
30.5.8. Control C - Normal Mode
30.5.9. Control C - Host SPI Mode
30.5.10. Baud Register
30.5.11. Control D
30.5.12. Debug Control Register
30.5.13. IrDA Control Register
30.5.14. IRCOM Transmitter Pulse Length Control Register
30.5.15. IRCOM Receiver Pulse Length Control Register
31. SPI - Serial Peripheral Interface
31.1. Features
31.2. Overview
31.2.1. Block Diagram
31.2.2. Signal Description
31.3. Functional Description
31.3.1. Initialization
31.3.2. Operation
31.3.2.1. Host Mode Operation
31.3.2.1.1. Normal Mode
31.3.2.1.2. Buffer Mode
31.3.2.1.3. SS Pin Functionality in Host Mode - Multi-Host Support
31.3.2.2. Client Mode
31.3.2.2.1. Normal Mode
31.3.2.2.2. Buffer Mode
31.3.2.2.3. SS Pin Functionality in Client Mode
31.3.2.3. Data Modes
31.3.2.4. Events
31.3.2.5. Interrupts
31.4. Register Summary
31.5. Register Description
31.5.1. Control A
31.5.2. Control B
31.5.3. Interrupt Control
31.5.4. Interrupt Flags - Normal Mode
31.5.5. Interrupt Flags - Buffer Mode
31.5.6. Data
32. TWI - Two-Wire Interface
32.1. Features
32.2. Overview
32.2.1. Block Diagram
32.2.2. Signal Description
32.3. Functional Description
32.3.1. General TWI Bus Concepts
32.3.2. TWI Basic Operation
32.3.2.1. Initialization
32.3.2.1.1. Host Initialization
32.3.2.1.2. Client Initialization
32.3.2.2. TWI Host Operation
32.3.2.2.1. Clock Generation
32.3.2.2.2. TWI Bus State Logic
32.3.2.2.3. Transmitting Address Packets
32.3.2.2.3.1. Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’
32.3.2.2.3.2. Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’
32.3.2.2.3.3. Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client
32.3.2.2.3.4. Case M4: Arbitration Lost or Bus Error
32.3.2.2.4. Transmitting Data Packets
32.3.2.2.5. Receiving Data Packets
32.3.2.3. TWI Client Operation
32.3.2.3.1. Receiving Address Packets
32.3.2.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set to ‘0’
32.3.2.3.1.2. Case S2: Address Packet Accepted - Direction Bit Set to ‘1’
32.3.2.3.1.3. Case S3: Stop Condition Received
32.3.2.3.1.4. Case S4: Collision
32.3.2.3.2. Receiving Data Packets
32.3.2.3.3. Transmitting Data Packets
32.3.3. Additional Features
32.3.3.1. SMBus
32.3.3.2. Multi-Host
32.3.3.3. Smart Mode
32.3.3.4. Dual Mode
32.3.3.5. Quick Command Mode
32.3.3.6. 10-bit Address
32.3.4. Interrupts
32.3.5. Sleep Mode Operation
32.3.6. Debug Operation
32.4. Register Summary
32.5. Register Description
32.5.1. Control A
32.5.2. Dual Mode Control Configuration
32.5.3. Debug Control
32.5.4. Host Control A
32.5.5. Host Control B
32.5.6. Host Status
32.5.7. Host Baud Rate
32.5.8. Host Address
32.5.9. Host Data
32.5.10. Client Control A
32.5.11. Client Control B
32.5.12. Client Status
32.5.13. Client Address
32.5.14. Client Data
32.5.15. Client Address Mask
33. CRCSCAN - Cyclic Redundancy Check Memory Scan
33.1. Features
33.2. Overview
33.2.1. Block Diagram
33.3. Functional Description
33.3.1. Initialization
33.3.2. Operation
33.3.2.1. Checksum
33.3.3. Interrupts
33.3.4. Sleep Mode Operation
33.3.5. Debug Operation
33.4. Register Summary
33.5. Register Description
33.5.1. Control A
33.5.2. Control B
33.5.3. Status
34. CCL - Configurable Custom Logic
34.1. Features
34.2. Overview
34.2.1. Block Diagram
34.2.2. Signal Description
34.2.2.1. CCL Input Selection MUX
34.3. Functional Description
34.3.1. Operation
34.3.1.1. Enable-Protected Configuration
34.3.1.2. Enabling, Disabling, and Resetting
34.3.1.3. Truth Table Logic
34.3.1.4. Truth Table Inputs Selection
34.3.1.5. Filter
34.3.1.6. Edge Detector
34.3.1.7. Sequencer Logic
34.3.1.8. Clock Source Settings
34.3.2. Interrupts
34.3.3. Events
34.3.4. Sleep Mode Operation
34.4. Register Summary
34.5. Register Description
34.5.1. Control A
34.5.2. Sequencer Control 0
34.5.3. Sequencer Control 1
34.5.4. Sequencer Control 2
34.5.5. Interrupt Control 0
34.5.6. Interrupt Control 1
34.5.7. Interrupt Flag
34.5.8. LUT n Control A
34.5.9. LUT n Control B
34.5.10. LUT n Control C
34.5.11. TRUTHn
35. AC - Analog Comparator
35.1. Features
35.2. Overview
35.2.1. Block Diagram
35.2.2. Signal Description
35.3. Functional Description
35.3.1. Initialization
35.3.2. Operation
35.3.2.1. Input Hysteresis
35.3.2.2. Input and Reference Selection
35.3.2.3. Normal Mode
35.3.2.4. Power Modes
35.3.2.5. Window Mode
35.3.3. Events
35.3.4. Interrupts
35.3.5. Sleep Mode Operation
35.4. Register Summary
35.5. Register Description
35.5.1. Control A
35.5.2. Control B
35.5.3. MUX Control
35.5.4. DAC Voltage Reference
35.5.5. Interrupt Control
35.5.6. Status
36. ADC - Analog-to-Digital Converter
36.1. Features
36.2. Overview
36.2.1. Block Diagram
36.2.2. Signal Description
36.3. Functional Description
36.3.1. Definitions
36.3.2. Initialization
36.3.3. Operation
36.3.3.1. Operation Modes
36.3.3.2. Starting a Conversion
36.3.3.3. Clock Generation
36.3.3.4. Conversion Timing
36.3.3.4.1. Single Conversion
36.3.3.4.2. Accumulated Conversion
36.3.3.4.3. Free-Running Conversion
36.3.3.4.4. Adjusting Conversion Time
36.3.3.5. Conversion Result (Output Formats)
36.3.3.6. Accumulation
36.3.3.7. Channel Selection
36.3.3.8. Temperature Measurement
36.3.3.9. Window Comparator
36.3.4. I/O Lines and Connections
36.3.5. Events
36.3.6. Interrupts
36.3.7. Debug Operation
36.3.8. Sleep Mode Operation
36.3.9. Synchronization
36.3.10. Configuration Change Protection
36.4. Register Summary
36.5. Register Description
36.5.1. Control A
36.5.2. Control B
36.5.3. Control C
36.5.4. Control D
36.5.5. Control E
36.5.6. Sample Control
36.5.7. MUX Selection for Positive ADC Input
36.5.8. MUX Selection for Negative ADC Input
36.5.9. Command
36.5.10. Event Control
36.5.11. Interrupt Control
36.5.12. Interrupt Flags
36.5.13. Debug Control
36.5.14. Temporary
36.5.15. Result
36.5.16. Window Comparator Low Threshold
36.5.17. Window Comparator High Threshold
37. DAC - Digital-to-Analog Converter
37.1. Features
37.2. Overview
37.2.1. Block Diagram
37.2.2. Signal Description
37.3. Functional Description
37.3.1. Initialization
37.3.2. Operation
37.3.2.1. Enabling, Disabling and Resetting
37.3.2.2. Starting a Conversion
37.3.2.3. DAC as Source For Internal Peripherals
37.3.2.4. DAC Output on Pin
37.3.3. Sleep Mode Operation
37.4. Register Summary
37.5. Register Description
37.5.1. Control A
37.5.2. DATA
38. OPAMP - Analog Signal Conditioning
38.1. Features
38.2. Overview
38.2.1. Block Diagram
38.2.2. Signal Description
38.3. Functional Description
38.3.1. Initialization
38.3.2. Operation
38.3.2.1. MUXPOS - Non-Inverting (+) Input Selection
38.3.2.2. MUXNEG - Inverting (-) Input Selection
38.3.2.3. MUXTOP, MUXBOT, MUXWIP - Resistor Ladder Configuration
38.3.2.4. Output Modes
38.3.2.5. Input Voltage Range
38.3.2.6. Internal Timer
38.3.2.7. Enable and Disable
38.3.2.8. Offset Calibration
38.3.3. Events
38.3.4. Interrupts
38.3.5. Sleep Mode Operation
38.3.6. Debug Operation
38.3.7. Application Usage
38.4. Register Summary
38.5. Register Description
38.5.1. Control A
38.5.2. Debug Control
38.5.3. Timebase
38.5.4. Power Control
38.5.5. Op Amp n Control A
38.5.6. Op Amp n Status
38.5.7. Op Amp n Resistor Ladder Multiplexer
38.5.8. Op Amp n Input Multiplexer
38.5.9. Op Amp n Settle Timer
38.5.10. Op Amp n Calibration
39. ZCD - Zero-Cross Detector
39.1. Features
39.2. Overview
39.2.1. Block Diagram
39.2.2. Signal Description
39.3. Functional Description
39.3.1. Initialization
39.3.2. Operation
39.3.2.1. External Resistor Selection
39.3.2.2. ZCD Logic Output
39.3.2.3. Correction for ZCPINV Offset
39.3.2.3.1. Correction By Offset Current
39.3.2.3.2. Correction by AC Coupling
39.3.2.4. Handling VPEAK Variations
39.3.3. Events
39.3.4. Interrupts
39.3.5. Sleep Mode Operation
39.4. Register Summary
39.5. Register Description
39.5.1. Control A
39.5.2. Interrupt Control
39.5.3. Status
40. UPDI - Unified Program and Debug Interface
40.1. Features
40.2. Overview
40.2.1. Block Diagram
40.2.2. Clocks
40.2.3. Physical Layer
40.2.4. Pinout Description
40.3. Functional Description
40.3.1. Principle of Operation
40.3.1.1. UPDI UART
40.3.1.2. BREAK Character
40.3.1.2.1. BREAK in One-Wire Mode
40.3.1.3. SYNCH Character
40.3.1.3.1. SYNCH in One-Wire Mode
40.3.2. Operation
40.3.2.1. UPDI Enabling
40.3.2.1.1. One-Wire Enable
40.3.2.1.1.1. UPDI Enable
40.3.2.2. UPDI Disabling
40.3.2.2.1. Disable During Start-Up
40.3.2.2.1.1. Time-Out Disable
40.3.2.2.1.2. Incorrect SYNCH Pattern
40.3.2.2.2. UPDI Regular Disable
40.3.2.3. UPDI Communication Error Handling
40.3.2.4. Direction Change
40.3.3. UPDI Instruction Set
40.3.3.1. LDS - Load Data from Data Space Using Direct Addressing
40.3.3.2. STS - Store Data to Data Space Using Direct Addressing
40.3.3.3. LD - Load Data from Data Space Using Indirect Addressing
40.3.3.4. ST - Store Data from UPDI to Data Space Using Indirect Addressing
40.3.3.5. LDCS - Load Data from Control and Status Register Space
40.3.3.6. STCS - Store Data to Control and Status Register Space
40.3.3.7. REPEAT - Set Instruction Repeat Counter
40.3.3.8. KEY - Set Activation Key or Send System Information Block
40.3.4. CRC Checking of Flash During Boot
40.3.5. Inter-Byte Delay
40.3.6. System Information Block
40.3.7. Enabling of Key Protected Interfaces
40.3.7.1. Chip Erase
40.3.7.2. NVM Programming
40.3.7.3. User Row Programming
40.3.8. Events
40.3.9. Sleep Mode Operation
40.4. Register Summary
40.5. Register Description
40.5.1. Status A
40.5.2. Status B
40.5.3. Control A
40.5.4. Control B
40.5.5. ASI Key Status
40.5.6. ASI Reset Request
40.5.7. ASI Control A
40.5.8. ASI System Control A
40.5.9. ASI System Status
40.5.10. ASI CRC Status
41. Instruction Set Summary
42. Electrical Characteristics
42.1. Disclaimer
42.2. Absolute Maximum Ratings
42.3. Standard Operating Conditions
42.4. DC Characteristics
42.4.1. Supply Voltage
42.4.2. Power Consumption
42.4.3. Peripherals Power Consumption
42.4.4. I/O Pin Characteristics
42.4.5. Memory Programming Specifications
42.4.6. Thermal Characteristics
42.5. AC Characteristics
42.5.1. Clock Parameters
42.5.1.1. Internal Oscillator Parameters
42.5.1.2. 32.768 kHz Crystal Oscillator (XOSC32K) Characteristics
42.5.1.3. High Frequency Crystal Oscillator (XOSCHF) Characteristics
42.5.1.4. External Clock Characteristics
42.5.1.5. PLL Specifications
42.5.2. Reset Controller Specifications
42.5.3. Internal Voltage Reference (VREF) Characteristics
42.5.4. TCD
42.5.5. USART
42.5.6. SPI
42.5.7. TWI
42.5.8. UPDI Timing
42.5.9. DAC Specifications
42.5.10. ADC Specifications
42.5.11. Analog Comparator Specifications
42.5.12. OPAMP Specifications
42.5.13. Zero-Cross Detector Specifications
43. Typical Characteristics
43.1. OPAMP
44. Ordering Information
45. Package Drawings
45.1. Online Package Drawings
45.2. 28-Pin SPDIP
45.3. 28-Pin SOIC
45.4. 28-Pin SSOP
45.5. 32-Pin VQFN
45.6. 32-Pin TQFP
45.7. 48-Pin VQFN
45.8. 48-Pin TQFP
45.9. 64-Pin VQFN
45.10. 64-Pin TQFP
46. Data Sheet Revision History
46.1. Rev.A - 02/2021
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