ADCLK
ADC Clock divider Register
Note:
ADC Clock divider is only available if F
OSC
is selected as the ADC clock source (CS =
0
).
Name:
ADCLK
Address:
0x1D2D
Reset:
Access:
Bit
7
6
5
4
3
2
1
0
CS[5:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bits 5:0 – CS[5:0]: ADC Clock divider Select
ADC Clock divider Select
Value
Description
n
ADC Clock frequency = F
OSC
/(2*(n+1))