CLCnSEL0
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D1S[5:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | x | x | x | x | x | x |
CLCn Data1 Input Selection
DyS | Input Source | DyS (cont.) | Input Source (cont.) |
---|---|---|---|
[0] 0000 0000 |
CLCIN0PPS | [21] 0001 0101 |
PWM3_OUT |
[1] 0000 0001 |
CLCIN1PPS | [22] 0001 0110 |
PWM4_OUT |
[2] 0000 0010 |
CLCIN2PPS | [23] 0001 0111 |
PWM5_OUT |
[3] 0000 0011 |
CLCIN3PPS | [24] 0001 1000 |
NCO1_OUT |
[4] 0000 0100 |
FOSC | [25] 0001 1001 |
C1_OUT |
[5] 0000 0101 |
HFINTOSC | [26] 0001 1010 |
ZCD_OUT |
[6] 0000 0110 |
LFINTOSC | [27] 0001 1011 |
IOC |
[7] 0000 0111 |
MFINTOSC (500 kHz) | [28] 0001 1100 |
CLC1_OUT |
[8] 0000 1000 |
MFINTOSC (32 kHz) | [29] 0001 1101 |
CLC2_OUT |
[9] 0000 1001 |
SFINTOSC (1 MHz) | [30] 0001 1110 |
CLC3_OUT |
[10] 0000 1010 |
SOSC | [31] 0001 1111 |
CLC4_OUT |
[11] 0000 1011 |
EXTOSC | [32] 0010 0000 |
TX1/CK1 |
[12] 0000 1100 |
ADCRC | [33] 0010 0001 |
TX2/CK2 |
[13] 0000 1101 |
TMR0_overflow | [34] 0010 0010 |
SDA1/SDO1 |
[14] 0000 1110 |
TMR1_overflow | [35] 0010 0011 |
SCL1/SCK1 |
[15] 0000 1111 |
TMR2_Postscaled_OUT | [36] 0010 0100 |
SDA2/SDO2 |
[16] 0001 0000 |
TMR3_overflow | [37] 0010 0101 |
SCL2/SCK2 |
[17] 0001 0001 |
TMR4_Postscaled_OUT | [38] 0010 0110 |
CWG1A_OUT |
[18] 0001 0010 |
TMR6_Postscaled_OUT | [39] 0010 0111 |
CWG1B_OUT |
[19] 0001 0011 |
CCP1_OUT | [40] 0010 1000 -
[63] 0011 1111 |
Reserved |
[20] 0001 0100 |
CCP2_OUT |