The output from a comparator can be synchronized with Timer1 by setting the SYNC bit.
Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a Race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. A simplified block diagram of the comparator module is shown in Figure 2. Refer to the “TMR1 - Timer1 Module with Gate Control” chapter for more details.