ADCON0
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ON | CONT | CS | FM | GO | |||
AccessR/W | R/W | R/W | R/W | R/W/HC/HS | |||
Reset0 | 0 | 0 | 0 | 0 |
ADC Enable
Value | Description |
---|---|
1 | ADC is enabled |
0 | ADC is disabled |
ADC Continuous Operation Enable
Value | Description |
---|---|
1 | GO is retriggered upon completion of each conversion trigger until ADTIF is set (if SOI is set) or until GO is cleared (regardless of the value of SOI) |
0 | ADC is cleared upon completion of each conversion trigger |
ADC Clock Selection
Value | Description |
---|---|
1 | Clock supplied from ADCRC dedicated oscillator |
0 | Clock supplied by FOSC, divided according to the ADCLK register |
ADC Results Format/Alignment Selection
Value | Description |
---|---|
1 | ADRES and ADPREV data are right justified |
0 | ADRES and ADPREV data are left justified |
ADC Conversion Status(1,2)
Value | Description |
---|---|
1 | ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the CONT bit. |
0 | ADC conversion completed/not in progress |