ADUTH
ADLTH and ADUTH are compared with ADERR to set the UTHR and LTHR bits. Depending on the setting of the TMD bits, an interrupt may be triggered by the results of this comparison.
Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UTH[15:8] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTH[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
ADC Upper Threshold - Signed two’s complement