In 10-bit Addressing mode, the first received byte is compared to
the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSbs of the 10-bit address
and stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the Update Address (
UA)
bit is set and SCL is held low until the user updates SSPxADD with the low address. The low
address byte is clocked in and all eight bits are compared to the low address value in
SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low
until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit
is cleared. This ensures the module is ready to receive the high address byte on the next
communication.
A high and low address match as a write request is required at the
start of all 10-bit addressing communication. A transmission can be initiated by issuing a
Restart once the client is addressed and clocking in the high address with the
WR/ bit set. The client hardware will then
acknowledge the read request and prepare to clock out data. This is only valid for a client
after it has received a complete high and low address byte match.