CONFIG2
1
’.Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DEBUG | STVREN | PPS1WAY | ZCD | BORV | DACAUTOEN | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOREN[1:0] | WDTE[1:0] | PWRTS[1:0] | MCLRE | ||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset1 | 1 | 1 | 1 | 1 | 1 | 1 |
Debugger Enable(1)
Value | Description |
---|---|
1 | Background debugger disabled |
0 | Background debugger enabled |
Stack Overflow/Underflow Reset Enable
Value | Description |
---|---|
1 | Stack Overflow or Underflow will cause a Reset |
0 | Stack Overflow or Underflow will not cause a Reset |
PPSLOCKED One-Way Set Enable
Value | Description |
---|---|
1 | The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCKED is set, all future changes to PPS registers are prevented |
0 | The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required) |
Zero-Cross Detect Disable
Value | Description |
---|---|
1 | ZCD disabled, ZCD can be enabled by setting the ZCDSEN bit of ZCDCON |
0 | ZCD always enabled |
Brown-Out Reset (BOR) Voltage Selection(2)
Value | Description |
---|---|
1 | Brown-out Reset voltage (VBOR) set to 1.9V |
0 | Brown-out Reset voltage (VBOR) set to 2.65V |
DAC Buffer Automatic Range Select Enable
Value | Description |
---|---|
1 | DAC Buffer reference range is determined by the REFRNG bit of DACxCON |
0 | DAC Buffer reference range is automatically determined by module hardware |
Brown-Out Reset (BOR) Enable(3)
Value | Description |
---|---|
11 | Brown-out Reset enabled, the SBOREN bit is ignored |
10 | Brown-out Reset enabled while running, disabled in Sleep; the SBOREN bit is ignored |
01 | Brown-out Reset enabled according to SBOREN |
00 | Brown-out Reset disabled |
Watchdog Timer (WDT) Enable
Value | Description |
---|---|
11 | WDT enabled regardless of Sleep; the SEN bit of WDTCON is ignored |
10 | WDT
enabled while Sleep = 0 , suspended when Sleep =
1 ; the SEN bit of WDTCON is
ignored |
01 | WDT enabled/disabled by the SEN bit of WDTCON |
00 | WDT disabled; SEN bit of WDTCON is ignored |
Power-Up Timer (PWRT) Selection
Value | Description |
---|---|
11 | PWRT disabled |
10 | PWRT is set at 64 ms |
01 | PWRT is set at 16 ms |
00 | PWRT is set at 1 ms |
Master Clear (MCLR) Enable
Value | Name | Description |
---|---|---|
x | If LVP = 1 |
MCLR pin is MCLR |
1 | If LVP = 0 |
MCLR pin is MCLR |
0 | If LVP = 0 |
MCLR pin function is port-defined function |