Host mode reception (see Figure 1) is enabled by setting the Receive Enable (RCEN)
bit.
Important: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each rollover, the
state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR.
After the falling edge of the eighth clock all the following events occur:
- RCEN is automatically cleared by
hardware.
- The contents of the SSPxSR are loaded
into the SSPxBUF.
- The BF flag bit is set.
- The SSPxIF flag bit is set.
- The Baud Rate Generator is suspended
from counting.
- The SCL pin is held low.
The MSSP is now in Idle state awaiting the next command. When the buffer is read by the
CPU, the BF flag bit is automatically cleared. The Host can then send an Acknowledge
sequence at the end of reception by setting the Acknowledge Sequence Enable (ACKEN)
bit.