CLCnGLS0
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| G1D4T | G1D4N | G1D3T | G1D3N | G1D2T | G1D2N | G1D1T | G1D1N |
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Resetx | x | x | x | x | x | x | x |
dyT: Gate1 Data ‘y’ True (noninverted)
| Value | Description |
|---|---|
| 1 | dyT is gated into g1 |
| 0 | dyT is not gated into g1 |
dyN: Gate1 Data ‘y’ Negated (inverted)
| Value | Description |
|---|---|
| 1 | dyN is gated into g1 |
| 0 | dyN is not gated into g1 |