Capacitive Voltage Divider (CVD) Features

The ADC module contains several features that allow the user to perform a relative capacitance measurement on any ADC channel using the internal ADC Sample-and-Hold capacitance as a reference. This relative capacitance measurement can be used to implement capacitive touch or proximity sensing applications. The following figure shows the basic block diagram of the CVD portion of the ADC module.

Figure 1. Hardware Capacitive Voltage Divider Block Diagram
This is an example to configure ADC for CVD operation:
  1. 1.Configure Port:
    1. a.Disable pin output driver (refer to the TRISx register)
    2. b.Configure pin as analog (refer to the ANSELx register)
  2. 2.Configure the ADC module:
    1. a.Select ADC conversion clock
    2. b.Configure voltage reference
    3. c.Select ADC input channel
    4. d.Configure precharge (ADPRE) and acquisition (ADACQ) time period
    5. e.Select precharge polarity (PPOL)
    6. f.Enable Double Sampling (DSEN)
    7. g.Turn on ADC module
  3. 3.Configure ADC interrupt (optional):
    1. a.Clear ADC interrupt flag
    2. b.Enable ADC interrupt
    3. c.Enable global interrupt (GIE bit)(1)
  4. 4.Start double sample conversion by setting the GO bit.
  5. 5.Wait for ADC conversion to complete by one of the following:
    • Polling the GO bit
    • Waiting for the ADC interrupt (if interrupt is enabled)
  6. 6.Second ADC conversion depends on the state of CONT:
    1. a.If CONT = 1, both conversion will repeat automatically form a single trigger.
    2. b.If CONT = 0, each conversion must be triggered separately.
  7. 7.The ADERR register contains the CVD result.
  8. 8.Clear the ADC interrupt flag (if interrupt is enabled).
Note:
  1. 1.With global interrupts disabled (GIE = 0), the device will wake from Sleep, but will not enter an Interrupt Service Routine.
Parent topic: Computation Operation