Pin Allocation Tables

Table 1. 14/16-Pin Allocation Table
I/O	14-Pin PDIP SOIC TSSOP	16-Pin VQFN	ADC	DAC	Comparator	ZCD	Timers	CCP	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	13	12	ANA0	—	C1IN0+	—	—	—	—	—	SS2⁽¹⁾	—	IOCA0	—	ICSPDAT ICDDAT
RA1	12	11	ANA1 V_REF+(ADC)	DAC1REF0+	C1IN0-	—	—	—	—	—	—	—	IOCA1	—	ICSPCLK ICDCLK
RA2	11	10	ANA2	DAC1REF0-	—	ZCD1	T0CKI⁽¹⁾	—	CWG1⁽¹⁾	—	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	3	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	2	ANA4	—	—	—	T1G⁽¹⁾	—	—	—	—	—	IOCA4	—	CLKOUT SOSCO
RA5	2	1	ANA5	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	—	CLCIN3⁽¹⁾	—	—	IOCA5	—	CLKIN SOSCI
RC0	10	9	ANC0	—	—	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	CK2^(1,3)	IOCC0	—	—
RC1	9	8	ANC1	—	C1IN1-	—	T4IN ⁽¹⁾	—	—	CLCIN2⁽¹⁾	SDA1^(1,3,4) SDI1^(1,3,4)	RX2⁽¹⁾ DT2^(1,3)	IOCC1	—	—
RC2	8	7	ANC2 ADACT⁽¹⁾	—	C1IN2-	—	T6IN ⁽¹⁾	—	—	—	—	—	IOCC2	—	—
RC3	7	6	ANC3	—	C1IN3-	—	—	CCP2⁽¹⁾	—	CLCIN0⁽¹⁾	SS1⁽¹⁾	—	IOCC3	—	—
RC4	6	5	ANC4	—	—	—	T3G⁽¹⁾	—	—	CLCIN1⁽¹⁾	SCL2^(1,3,4) SCK2^(1,3,4)	CK1^(1,3)	IOCC4	—	—
RC5	5	4	ANC5	—	—	—	T3CKI⁽¹⁾	CCP1⁽¹⁾	—	—	SDA2^(1,3,4) SDI2^(1,3,4)	RX1⁽¹⁾ DT1^(1,3)	IOCC5	—	—
V_DD	1	16	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	14	13	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	DAC1OUT1	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Notes: 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. 2.All output signals shown in this row are PPS remappable. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. 4.These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table 2. 20-Pin Allocation Table
I/O	20-Pin PDIP SOIC SSOP	20-Pin QFN	ADC	DAC	Comparator	ZCD	Timers	CCP	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	19	16	ANA0	—	C1IN0+	—	—	—	—	—	—	—	IOCA0	—	ICSPDAT ICDDAT
RA1	18	15	ANA1 V_REF+(ADC)	DAC1REF0+	C1IN0-	—	—	—	—	—	SS2⁽¹⁾	—	IOCA1	—	ICSPCLK ICDCLK
RA2	17	14	ANA2	DAC1REF0-	—	ZCD1	T0CKI⁽¹⁾	—	CWG1⁽¹⁾	CLCIN0⁽¹⁾	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	1	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	20	ANA4	—	—	—	T1G⁽¹⁾	—	—	—	—	—	IOCA4	—	CLKOUT SOSCO
RA5	2	19	ANA5	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	—	—	—	—	IOCA5	—	CLKIN SOSCI
RB4	13	10	ANB4	—	—	—	—	—	—	CLCIN2⁽¹⁾	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCB4	—	—
RB5	12	9	ANB5	—	—	—	—	—	—	CLCIN3⁽¹⁾	SDA2^(1,3,4) SDI2^(1,3,4)	RX1⁽¹⁾ DT1^(1,3)	IOCB5	—	—
RB6	11	8	ANB6	—	—	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCB6	—	—
RB7	10	7	ANB7	—	—	—	—	—	—	—	SCL2^(1,3,4) SCK2^(1,3,4)	CK1^(1,3)	IOCB7	—	—
RC0	16	13	ANC0	—	—	—	—	—	—	—	—	CK2^(1,3)	IOCC0	—	—
RC1	15	12	ANC1	—	C1IN1-	—	T4IN⁽¹⁾	—	—	—	—	RX2⁽¹⁾ DT2^(1,3)	IOCC1	—	—
RC2	14	11	ANC2 ADACT⁽¹⁾	—	C1IN2-	—	T6IN⁽¹⁾	—	—	—	—	—	IOCC2	—	—
RC3	7	4	ANC3	—	C1IN3-	—	—	CCP2⁽¹⁾	—	CLCIN1⁽¹⁾	—	—	IOCC3	—	—
RC4	6	3	ANC4	—	—	—	T3G⁽¹⁾	—	—	—	—	—	IOCC4	—	—
RC5	5	2	ANC5	—	—	—	T3CKI⁽¹⁾	CCP1⁽¹⁾	—	—	—	—	IOCC5	—	—
RC6	8	5	ANC6	—	—	—	—	—	—	—	SS1⁽¹⁾	—	IOCC6	—	—
RC7	9	6	ANC7	—	—	—	—	—	—	—	—	—	IOCC7	—	—
V_DD	1	18	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	20	17	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	DAC1OUT1	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Notes: 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. 2.All output signals shown in this row are PPS remappable. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. 4.These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.