In Multi-Host mode, the interrupt generation on the detection of the
Start and Stop conditions allows the determination of when the bus is free. The Stop (
P) and
Start (
S) bits are cleared from a Reset or when the MSSP module is disabled. Control of
the I
2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits cleared. When the bus is busy, enabling the MSSP
interrupt will generate an interrupt when the Stop condition occurs.
In Multi-Host operation, the SDA line must be monitored for
arbitration to see if the signal level is the expected output level. This check is
performed by hardware with the result placed in the BCLxIF bit.
The states where arbitration can be lost are:
- Address Transfer
- Data Transfer
- A Start Condition
- A Repeated Start Condition
- An Acknowledge Condition