PIR3
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCL1IF | SSP1IF | RC2IF | TX2IF | RC1IF | TX1IF | CLC4IF | CLC3IF |
AccessR/W/HS | R/W/HS | R | R | R | R | R/W/HS | R/W/HS |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
MSSP1 Bus Collision Interrupt Flag
Value | Description |
---|---|
1 | An MSSP1 Bus Collision was detected (must be cleared in software) |
0 | No MSSP1 Bus Collision event was detected |
MSSP1 Interrupt Flag
Value | Description |
---|---|
1 | MSSP1 interrupt has occurred (must be cleared in software) |
0 | MSSP1 interrupt event has not occurred |
EUSART2 Receive Interrupt Flag(1)
Value | Description |
---|---|
1 | The EUSART2 receive buffer (RC2REG) is not empty (contains at least one byte) |
0 | The EUSART2 receive buffer is empty |
EUSART2 Transmit Interrupt Flag(2)
Value | Description |
---|---|
1 | The EUSART2 transmit buffer (TX2REG) is empty |
0 | The EUSART2 transmit buffer is not empty |
EUSART1 Receive Interrupt Flag(3)
Value | Description |
---|---|
1 | The EUSART1 receive buffer (RC1REG) is not empty (contains at least one byte) |
0 | The EUSART1 receive buffer is empty |
EUSART1 Transmit Interrupt Flag(4)
Value | Description |
---|---|
1 | The EUSART1 transmit buffer (TX1REG) is empty |
0 | The EUSART1 transmit buffer is not empty |
CLC4 Interrupt Flag
Value | Description |
---|---|
1 | CLC4 interrupt has occurred (must be cleared in software) |
0 | CLC4 interrupt event has not occurred |
CLC3 Interrupt Flag
Value | Description |
---|---|
1 | CLC3 interrupt has occurred (must be cleared in software) |
0 | CLC3 interrupt event has not occurred |