At the end of each computation:
- The conversion results are captured at
the end-of-conversion.
- The error (ADERR) is
calculated based on a difference calculation which is selected by the CALC bits. The value can be one of the following
calculations:
- The first derivative of single
measurements
- The CVD result when double
sampling is enabled
- The current result vs. setpoint
value in the ADSTPT register
- The current result vs. the
filtered/average result
- The first derivative of the
filtered/average value
- Filtered/average value vs.
setpoint value in the ADSTPT register
- The result of the calculation (ADERR) is
compared to the upper and lower thresholds, ADUTH and
ADLTH registers, to set the UTHR and LTHR Status bits. The threshold logic is selected by the TMD bits. The threshold trigger option can be one of the following:
- Never interrupt
- Error is less than lower
threshold
- Error is greater than or equal to
lower threshold
- Error is between thresholds
(inclusive)
- Error is outside of
thresholds
- Error is less than or equal to
upper threshold
- Error is greater than upper
threshold
- Always interrupt regardless of
threshold test results
- If the Threshold condition is
met, the channel threshold interrupt flag ADCHxIF is set.
Important:
- The threshold tests are signed
operations.
- If the AOV bit is set, a threshold interrupt is signaled. It is good
practice for threshold interrupt handlers to verify the validity of the
threshold by checking the AOV bit.