Contents

PIC16F180 Family Summary

Operating Characteristics

Power-Saving Functionality

Digital Peripherals

Analog Peripherals

Clocking Structure

Programming/Debug Features

5. Pin Diagrams

6. Pin Allocation Tables

7. Guidelines for Getting Started with PIC16F180 Microcontrollers

7.1. Basic Connection Requirements

7.2. Power Supply Pins

7.2.1. Decoupling Capacitors

7.2.2. Tank Capacitors

7.3. Master Clear (MCLR) Pin

7.4. In-Circuit Serial Programming (ICSP) Pins

7.5. Unused I/Os

8. Register and Bit Naming Conventions

8.1. Register Names

8.2.1. Short Bit Names

8.2.2. Long Bit Names

8.2.3. Bit Fields

8.3. Register and Bit Naming Exceptions

8.3.1. Status, Interrupt and Mirror Bits

9. Register Legend

10. Enhanced Mid-Range CPU

10.1. Automatic Interrupt Context Saving

10.2. 16-Level Stack with Overflow and Underflow

10.3. File Select Registers

10.4. Instruction Set

11. Device Configuration

11.1. Configuration Words

11.2. Code Protection

11.3. Write Protection

11.5. Device ID and Revision ID

11.6. Register Definitions: Configuration Settings

11.6.1. CONFIG1

11.6.2. CONFIG2

11.6.3. CONFIG3

11.6.4. CONFIG4

11.6.5. CONFIG5

11.7. Register Definitions: Device ID and Revision ID

11.7.1. Device ID

11.7.2. Revision ID

12. Memory Organization

12.1. Program Memory Organization

12.1.1. Reading Program Memory as Data

12.1.1.1. RETLW Instruction

12.1.1.2. Indirect Read with FSR

12.1.2. Memory Access Partition (MAP)

12.1.2.1. Application Block

12.1.2.2. Boot Block

12.1.2.3. Storage Area Flash

12.1.2.4. Memory Write Protection

12.1.2.5. Memory Violation

12.1.3. Device Information Area (DIA)

12.1.3.1. Microchip Unique Identifier (MUI)

12.1.3.2. External Unique Identifier (EUI)

12.1.3.3. Standard Parameters for the Temperature Sensor

12.1.3.4. Fixed Voltage Reference Data

12.1.4. Device Configuration Information (DCI)

12.1.4.1. DIA and DCI Access

12.2. Data Memory Organization

12.2.1. Bank Selection

12.2.2. Core Registers

12.2.3. Special Function Register

12.2.4. General Purpose RAM

12.2.5. Common RAM

12.2.6. Device Memory Maps

12.3. STATUS Register

12.4. PCL and PCLATH

12.4.1. Modifying PCL

12.4.2. Computed GOTO

12.4.3. Computed Function Calls

12.4.4. Branching

12.5.1. Accessing the Stack

12.5.2. Overflow/Underflow Reset

12.6. Indirect Addressing

12.6.1. Traditional/Banked Data Memory

12.6.2. Linear Data Memory

12.6.3. Program Flash Memory

12.6.4. Data EEPROM Memory

12.7. Register Definitions: Memory Organization

12.8. Register Summary - Memory Organization

13.1. Power-on Reset (POR)

13.1.1. Programming Mode Exit

13.2. Brown-out Reset (BOR)

13.2.1. BOR Is Always On

13.2.2. BOR Is Off in Sleep

13.2.3. BOR Controlled by Software

13.2.4. BOR Is Always Off

13.3. MCLR Reset

13.3.1. MCLR Enabled

13.3.2. MCLR Disabled

13.4. Watchdog Timer (WDT) Reset

13.5. RESET Instruction

13.6. Stack Overflow/Underflow Reset

13.7. Power-Up Timer (PWRT)

13.8. Start-Up Sequence

13.9. Memory Execution Violation

13.10. Determining the Cause of a Reset

13.11. Power Control (PCONx) Register

13.12. Register Definitions: Power Control

13.12.1. BORCON

13.13. Register Summary - Power Control

14. OSC - Oscillator Module

14.1. Clock Source Types

14.1.1. External Clock Sources

14.1.1.1. EC Mode

14.1.1.2. Secondary Oscillator

14.1.1.2.1. SOSC Start-Up Timing

14.1.2. Internal Clock Sources

14.1.2.1. HFINTOSC

14.1.2.1.1. HFINTOSC Frequency Tuning

14.1.2.2. MFINTOSC

14.1.2.3. SFINTOSC

14.1.2.4. LFINTOSC

14.1.2.5. ADCRC

14.1.3. Oscillator Status and Manual Enable

14.2. Active Clock Tuning (ACT)

14.2.1. ACT Lock Status

14.2.2. ACT Out-Of-Range Status

14.2.3. ACT Update Disable

14.2.4. ACT Interrupts

14.3. Register Definitions: Oscillator Module

14.3.2. OSCCON2

14.3.3. OSCCON3

14.3.4. OSCTUNE

14.3.6. OSCSTAT

14.4. Register Summary - Oscillator Module

15. INT - Interrupts

15.2. INTCON Register

15.3. PIE Registers

15.4. PIR Registers

15.5. Operation

15.6. Interrupt Latency

15.7. Interrupts During Sleep

15.9. Automatic Context Saving

15.10. Register Definitions: Interrupt Control

15.10.1. INTCON

15.11. Register Summary - Interrupt Control

16.1. Sleep Mode Operation

16.1.1. Wake-Up from Sleep

16.1.2. Wake-Up Using Interrupts

17. WDT - Watchdog Timer

17.1. Selectable Clock Sources

17.2. WDT Operating Modes

17.2.1. WDT Is Always On

17.2.2. WDT Is Off During Sleep

17.2.3. WDT Controlled by Software

17.2.4. WDT Is Off

17.3. WDT Time-Out Period

17.4. Clearing the WDT

17.5. WDT Operation During Sleep

17.6. Register Definitions: WDT Control

17.7. Register Summary - WDT Control

18. NVM - Nonvolatile Memory Control

18.1. Program Flash Memory (PFM)

18.1.1. FSR and INDF Access

18.1.1.1. FSR Read

18.1.1.2. FSR Write

18.1.2. NVMREG Access

18.1.2.1. NVMREG Read Operation

18.1.2.2. NVM Unlock Sequence

18.1.2.3. NVMREG Erase of Program Memory

18.1.2.4. NVMREG Write to Program Memory

18.1.2.5. Modifying Flash Program Memory

18.1.2.6. NVMREG Access to DIA, DCI, User ID, Device ID, Revision ID, and Configuration Words

18.1.2.7. Write Verify

18.1.2.8. WRERR Bit

18.2. Data Flash Memory (DFM)

18.2.1. FSR and INDF Access

18.2.1.1. FSR DFM Read

18.2.1.2. FSR DFM Write

18.2.2. NVMREG Access

18.2.2.1. NVMREG Read Operation

18.2.2.2. NVM Unlock Sequence

18.2.2.3. NVMREG Erase of DFM

18.2.2.4. NVMREG Write to DFM

18.2.2.5. WRERR Bit

18.3. Register Definitions: Nonvolatile Memory Control

18.3.3. NVMCON1

18.3.4. NVMCON2

18.4. Register Summary - NVM Control

19.2. PORTx - Data Register

19.3. LATx - Output Latch

19.4. TRISx - Direction Control

19.5. ANSELx - Analog Control

19.6. WPUx - Weak Pull-Up Control

19.7. INLVLx - Input Threshold Control

19.8. SLRCONx - Slew Rate Control

19.9. ODCONx - Open-Drain Control

19.10. Edge Selectable Interrupt-on-Change

19.11. I2C Pad Control

19.12. I/O Priorities

19.13. MCLR/VPP/RA3 Pin

19.14. Register Definitions: Port Control

19.14.4. ANSELx

19.14.6. INLVLx

19.14.7. SLRCONx

19.14.8. ODCONx

19.14.9. RxyI2C

19.15. Register Summary - IO Ports

20. IOC - Interrupt-on-Change

20.2. Enabling the Module

20.3. Individual Pin Configuration

20.4. Interrupt Flags

20.5. Clearing Interrupt Flags

20.6. Operation in Sleep

20.7. Register Definitions: Interrupt-on-Change Control

20.8. Register Summary - Interrupt-on-Change

21. PPS - Peripheral Pin Select Module

21.2. PPS Inputs

21.3. PPS Outputs

21.4. Bidirectional Pins

21.5.1. PPS One-Way Lock

21.6. Operation During Sleep

21.7. Effects of a Reset

21.8. Register Definitions: Peripheral Pin Select (PPS)

21.8.3. PPSLOCK

21.9. Register Summary - Peripheral Pin Select Module

22. TMR0 - Timer0 Module

22.1. Timer0 Operation

22.1.1. 8-Bit Mode

22.1.2. 16-Bit Mode

22.2. Clock Selection

22.2.1. Synchronous Mode

22.2.2. Asynchronous Mode

22.2.3. Programmable Prescaler

22.2.4. Programmable Postscaler

22.3. Timer0 Output and Interrupt

22.3.1. Timer0 Output

22.3.2. Timer0 Interrupt

22.3.3. Timer0 Example

22.4. Operation During Sleep

22.5. Register Definitions: Timer0 Control

22.6. Register Summary - Timer0

23. TMR1 - Timer1 Module with Gate Control

23.1. Timer1 Operation

23.2. Clock Source Selection

23.2.1. Internal Clock Source

23.2.2. External Clock Source

23.3. Timer1 Prescaler

23.4. Secondary Oscillator

23.5. Timer1 Operation in Asynchronous Counter Mode

23.5.1. Reading and Writing TMRx in Asynchronous Counter Mode

23.6. Timer1 16-Bit Read/Write Mode

23.7. Timer1 Gate

23.7.1. Timer1 Gate Enable

23.7.2. Timer1 Gate Source Selection

23.7.3. Timer1 Gate Toggle Mode

23.7.4. Timer1 Gate Single Pulse Mode

23.7.5. Timer1 Gate Value Status

23.7.6. Timer1 Gate Event Interrupt

23.8. Timer1 Interrupt

23.9. Timer1 Operation During Sleep

23.10. CCP Capture/Compare Time Base

23.11. CCP Special Event Trigger

23.12. Register Definitions: Timer1 Control

23.12.2. TxGCON

23.12.4. TxGATE

23.13. Register Summary - Timer1

24. TMR2 - Timer2 Module

24.1. Timer2 Operation

24.1.1. Free-Running Period Mode

24.1.2. One Shot Mode

24.1.3. Monostable Mode

24.2. Timer2 Output

24.3. External Reset Sources

24.4. Timer2 Interrupt

24.5. PSYNC Bit

24.6. CSYNC Bit

24.7. Operating Modes

24.8. Operation Examples

24.8.1. Software Gate Mode

24.8.2. Hardware Gate Mode

24.8.3. Edge Triggered Hardware Limit Mode

24.8.4. Level Triggered Hardware Limit Mode

24.8.5. Software Start One Shot Mode

24.8.6. Edge Triggered One Shot Mode

24.8.7. Edge Triggered Hardware Limit One Shot Mode

24.8.8. Level Reset, Edge Triggered Hardware Limit One Shot Modes

24.8.9. Edge Triggered Monostable Modes

24.8.10. Level Triggered Hardware Limit One Shot Modes

24.9. Timer2 Operation During Sleep

24.10. Register Definitions: Timer2 Control

24.10.5. TxCLKCON

24.11. Register Summary - Timer2

25. NCO - Numerically Controlled Oscillator Module

25.1. NCO Operation

25.1.1. NCO Clock Sources

25.1.2. Accumulator

25.1.4. Increment Registers

25.2. Fixed Duty Cycle Mode

25.3. Pulse Frequency Mode

25.4. Output Polarity Control

25.5. Interrupts

25.6. Effects of a Reset

25.7. Operation in Sleep

25.8. Register Definitions: NCO

25.8.1. NCOxCON

25.8.2. NCOxCLK

25.8.3. NCOxACC

25.8.4. NCOxINC

25.9. Register Summary - NCO

26. CWG - Complementary Waveform Generator Module

26.1. Fundamental Operation

26.2. Operating Modes

26.2.1. Half Bridge Mode

26.2.2. Push-Pull Mode

26.2.3. Full Bridge Mode

26.2.3.1. Direction Change in Full Bridge Mode

26.2.3.2. Dead-Band Delay in Full Bridge Mode

26.2.4. Steering Modes

26.2.4.1. Synchronous Steering Mode

26.2.4.2. Asynchronous Steering Mode

26.2.4.3. Start-Up Considerations

26.3. Clock Source

26.4. Selectable Input Sources

26.5. Output Control

26.5.1. CWG Output

26.5.2. Polarity Control

26.6. Dead-Band Control

26.6.1. Dead-Band Functionality in Half Bridge Mode

26.6.2. Dead-Band Functionality in Full Bridge Mode

26.7. Rising Edge and Reverse Dead Band

26.8. Falling Edge and Forward Dead Band

26.9. Dead-Band Jitter

26.10. Auto-Shutdown

26.10.1. Shutdown

26.10.2. Software Generated Shutdown

26.10.3. External Input Source

26.10.4. Pin Override Levels

26.10.5. Auto-Shutdown Interrupts

26.11. Auto-Shutdown Restart

26.11.1. Software-Controlled Restart

26.11.2. Auto-Restart

26.12. Operation During Sleep

26.13. Configuring the CWG

26.14. Register Definitions: CWG Control

26.14.1. CWGxCON0

26.14.2. CWGxCON1

26.14.3. CWGxCLK

26.14.4. CWGxISM

26.14.5. CWGxSTR

26.14.6. CWGxAS0

26.14.7. CWGxAS1

26.14.8. CWGxDBR

26.14.9. CWGxDBF

26.15. Register Summary - CWG

27. CCP - Capture/Compare/PWM Module

27.1. CCP Module Configuration

27.1.1. CCP Modules and Timer Resources

27.1.2. Open-Drain Output Option

27.2. Capture Mode

27.2.1. Capture Sources

27.2.2. Timer1 Mode for Capture

27.2.3. Software Interrupt Mode

27.2.4. CCP Prescaler

27.2.5. Capture During Sleep

27.3. Compare Mode

27.3.1. CCPx Pin Configuration

27.3.2. Timer1 Mode for Compare

27.3.3. Compare During Sleep

27.4. PWM Overview

27.4.1. Standard PWM Operation

27.4.2. Setup for PWM Operation

27.4.3. Timer2 Timer Resource

27.4.4. PWM Period

27.4.5. PWM Duty Cycle

27.4.6. PWM Resolution

27.4.7. Operation in Sleep Mode

27.4.8. Changes in System Clock Frequency

27.4.9. Effects of Reset

27.5. Register Definitions: CCP Control

27.5.1. CCPxCON

27.5.2. CCPxCAP

27.6. Register Summary - CCP Control

28. Capture, Compare, and PWM Timers Selection

28.1. Register Definitions: Capture, Compare, and PWM Timers Selection

28.1.1. CCPTMRS0

28.2. Register Summary - Capture, Compare, and PWM Timers Selection

29. PWM - Pulse-Width Modulation

29.1. Fundamental Operation

29.2. PWM Output Polarity

29.3. PWM Period

29.4. PWM Duty Cycle

29.5. PWM Resolution

29.6. Operation in Sleep Mode

29.7. Changes in System Clock Frequency

29.8. Effects of Reset

29.9. Setup for PWM Operation Using PWMx Output Pins

29.9.1. PWMx Pin Configuration

29.10. Setup for PWM Operation to Other Device Peripherals

29.11. Register Definitions: PWM Control

29.11.1. PWMxCON

29.11.2. PWMxDC

29.12. Register Summary - PWM

30. PWM Timers Selection

30.1. Register Definitions: Capture, Compare, and PWM Timers Selection

30.1.1. PWMTMRS0

30.2. Register Summary - Capture, Compare, and PWM Timers Selection

31. CLC - Configurable Logic Cell

31.1. CLC Setup

31.1.1. Data Selection

31.1.2. Data Gating

31.1.3. Logic Function

31.1.4. Output Polarity

31.2. CLC Interrupts

31.3. Effects of a Reset

31.4. Output Mirror Copies

31.5. Operation During Sleep

31.6. CLC Setup Steps

31.7. Register Overlay

31.8. Register Definitions: Configurable Logic Cell

31.8.1. CLCSELECT

31.8.2. CLCnCON

31.8.3. CLCnPOL

31.8.4. CLCnSEL0

31.8.5. CLCnSEL1

31.8.6. CLCnSEL2

31.8.7. CLCnSEL3

31.8.8. CLCnGLS0

31.8.9. CLCnGLS1

31.8.10. CLCnGLS2

31.8.11. CLCnGLS3

31.8.12. CLCDATA

31.9. Register Summary - CLC Control

32. MSSP - Host Synchronous Serial Port Module

32.1. SPI Mode Overview

32.1.1. SPI Mode Registers

32.1.2. SPI Mode Operation

32.1.2.1. SPI Host Mode

32.1.2.2. SPI Client Mode

32.1.2.3. Daisy-Chain Configuration

32.1.2.4. Client Select Synchronization

32.1.2.5. SPI Operation in Sleep Mode

32.2. I2C Mode Overview

32.2.1. I2C Mode Registers

32.2.2. I2C Mode Operation

32.2.2.1. Definition of I2C Terminology

32.2.2.2. Byte Format

32.2.2.3. SDA and SCL Pins

32.2.2.4. SDA Hold Time

32.2.2.5. Clock Stretching

32.2.2.6. Arbitration

32.2.2.7. Start Condition

32.2.2.8. Stop Condition

32.2.2.9. Start/Stop Condition Interrupt Masking

32.2.2.10. Restart Condition

32.2.2.11. Acknowledge Sequence

32.2.3. I2C Client Mode Operation

32.2.3.1. Client Mode Addresses

32.2.3.1.1. I2C Client 7-Bit Addressing Mode

32.2.3.1.2. I2C Client 10-Bit Addressing Mode

32.2.3.2. Clock Stretching

32.2.3.2.1. Normal Clock Stretching

32.2.3.2.2. 10-Bit Addressing Mode

32.2.3.2.3. Byte NACKing

32.2.3.3. Clock Synchronization and the CKP Bit

32.2.3.4. General Call Address Support

32.2.3.5. SSP Mask Register

32.2.3.6. Client Reception

32.2.3.6.1. 7-Bit Addressing Reception

32.2.3.6.2. 7-Bit Reception with AHEN and DHEN

32.2.3.6.3. Client Mode 10-Bit Address Reception

32.2.3.6.4. 10-Bit Addressing with Address or Data Hold

32.2.3.7. Client Transmission

32.2.3.7.1. Client Mode Bus Collision

32.2.3.7.2. 7-Bit Transmission

32.2.3.7.3. 7-Bit Transmission with Address Hold Enabled

32.2.4. I2C Host Mode

32.2.4.1. I2C Host Mode Operation

32.2.4.1.1. Clock Arbitration

32.2.4.1.2. WCOL Status Flag

32.2.4.1.3. I2C Host Mode Start Condition Timing

32.2.4.1.4. I2C Host Mode Repeated Start Condition Timing

32.2.4.1.5. Acknowledge Sequence Timing

32.2.4.1.5.1. Acknowledge Write Collision

32.2.4.1.6. Stop Condition Timing

32.2.4.1.6.1. Write Collision on Stop

32.2.4.1.7. Sleep Operation

32.2.4.1.8. Effects of a Reset

32.2.4.2. I2C Host Mode Transmission

32.2.4.2.1. BF Status Flag

32.2.4.2.2. WCOL Status Flag

32.2.4.2.3. ACKSTAT Status Flag

32.2.4.2.4. Typical Transmit Sequence

32.2.4.3. I2C Host Mode Reception

32.2.4.3.1. BF Status Flag

32.2.4.3.2. SSPOV Status Flag

32.2.4.3.3. WCOL Status Flag

32.2.4.3.4. Typical Receive Sequence

32.2.5. Multi-Host Mode

32.2.5.1. Multi-Host Communication, Bus Collision and Bus Arbitration

32.2.5.1.1. Bus Collision During a Start Condition

32.2.5.1.2. Bus Collision During a Repeated Start Condition

32.2.5.1.3. Bus Collision During a Stop Condition

32.3. Baud Rate Generator

32.4. Register Definitions: MSSP Control

32.4.1. SSPxBUF

32.4.2. SSPxADD

32.4.3. SSPxMSK

32.4.4. SSPxSTAT

32.4.5. SSPxCON1

32.4.6. SSPxCON2

32.4.7. SSPxCON3

32.5. Register Summary - MSSP Control

33. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter

33.1. EUSART Asynchronous Mode

33.1.1. EUSART Asynchronous Transmitter

33.1.1.1. Enabling the Transmitter

33.1.1.2. Transmitting Data

33.1.1.3. Transmit Data Polarity

33.1.1.4. Transmit Interrupt Flag

33.1.1.5. TSR Status

33.1.1.6. Transmitting 9-Bit Characters

33.1.1.7. Asynchronous Transmission Setup

33.1.2. EUSART Asynchronous Receiver

33.1.2.1. Enabling the Receiver

33.1.2.2. Receiving Data

33.1.2.3. Receive Interrupts

33.1.2.4. Receive Framing Error

33.1.2.5. Receive Overrun Error

33.1.2.6. Receiving 9-Bit Characters

33.1.2.7. Address Detection

33.1.2.8. Asynchronous Reception Setup

33.1.2.9. 9-Bit Address Detection Mode Setup

33.2. Clock Accuracy with Asynchronous Operation

33.3. EUSART Baud Rate Generator (BRG)

33.3.1. Auto-Baud Detect

33.3.2. Auto-Baud Overflow

33.3.3. Auto-Wake-Up on Break

33.3.3.1. Special Considerations

33.3.4. Break Character Sequence

33.3.4.1. Break and Sync Transmit Sequence

33.3.5. Receiving a Break Character

33.4. EUSART Synchronous Mode

33.4.1. Synchronous Host Mode

33.4.1.1. Host Clock

33.4.1.2. Clock Polarity

33.4.1.3. Synchronous Host Transmission

33.4.1.4. Synchronous Host Transmission Setup

33.4.1.5. Synchronous Host Reception

33.4.1.6. Client Clock

33.4.1.7. Receive Overrun Error

33.4.1.8. Receiving 9-Bit Characters

33.4.1.9. Synchronous Host Reception Setup

33.4.2. Synchronous Client Mode

33.4.2.1. EUSART Synchronous Client Transmit

33.4.2.2. Synchronous Client Transmission Setup

33.4.2.3. EUSART Synchronous Client Reception

33.4.2.4. Synchronous Client Reception Setup

33.5. EUSART Operation During Sleep

33.5.1. Synchronous Receive During Sleep

33.5.2. Synchronous Transmit During Sleep

33.6. Register Definitions: EUSART Control

33.6.3. BAUDxCON

33.7. Register Summary - EUSART

34. ADC - Analog-to-Digital Converter with Computation Module

34.1. ADC Configuration

34.1.1. Port Configuration

34.1.2. Channel Selection

34.1.2.1. Channel Grouping

34.1.3. ADC Voltage Reference

34.1.4. Conversion Clock

34.1.5. Interrupts

34.1.6. Result Formatting

34.2. ADC Operation

34.2.1. Starting a Conversion

34.2.2. Completion of a Conversion

34.2.3. ADC Operation During Sleep

34.2.4. External Trigger During Sleep

34.2.5. Auto-Conversion Trigger

34.2.6. ADC Conversion Procedure (Basic Mode)

34.3. ADC Acquisition Requirements

34.4. Computation Operation

34.4.1. Digital Filter/Average

34.4.2. Basic Mode

34.4.3. Accumulate Mode

34.4.4. Average Mode

34.4.5. Burst Average Mode

34.4.6. Low-Pass Filter Mode

34.4.7. Threshold Comparison

34.4.8. Repetition and Sampling Options

34.4.8.1. Continuous Sampling Mode

34.4.8.2. Double Sample Conversion

34.4.9. Capacitive Voltage Divider (CVD) Features

34.4.9.1. CVD Operation

34.4.9.2. Precharge Control

34.4.9.3. Acquisition Control for CVD (ADPRE > 0)

34.4.9.4. Guard Ring Outputs

34.4.9.5. Additional Sample-and-Hold Capacitance

34.5. Register Definitions: ADC Control

34.5.14. ADFLTR

34.5.16. ADPREV

34.5.18. ADSTPT

34.5.23. ADCGxA

34.5.24. ADCGxB

34.5.25. ADCGxC

34.6. Register Summary - ADC

35. DAC - Digital-to-Analog Converter Module

35.1. Output Voltage Selection

35.2. Ratiometric Output Level

35.3. Buffered DAC Output Range Selection

35.4. Operation During Sleep

35.5. Effects of a Reset

35.6. Register Definitions: DAC Control

35.6.1. DACxCON

35.6.2. DACxDATL

35.7. Register Summary - DAC

36. CMP - Comparator Module

36.1. Comparator Overview

36.2. Comparator Control

36.2.1. Comparator Enable

36.2.2. Comparator Output

36.2.3. Comparator Output Polarity

36.3. Comparator Output Synchronization

36.4. Comparator Hysteresis

36.5. Comparator Interrupt

36.6. Comparator Positive Input Selection

36.7. Comparator Negative Input Selection

36.8. Comparator Response Time

36.9. Analog Input Connection Considerations

36.10. Operation in Sleep Mode

36.11. ADC Auto-Trigger Source

36.12. Register Definitions: Comparator Control

36.12.1. CMxCON0

36.12.2. CMxCON1

36.12.3. CMxNCH

36.12.4. CMxPCH

36.13. Register Summary - Comparator

37. FVR - Fixed Voltage Reference

37.1. Independent Gain Amplifiers

37.2. FVR Stabilization Period

37.3. Register Definitions: FVR

37.4. Register Summary - FVR

38. Temperature Indicator Module

38.1. Module Operation

38.1.1. Temperature Indicator Range

38.1.2. Minimum Operating VDD

38.2. Temperature Calculation

38.3. ADC Acquisition Time

38.4. Register Definitions: Temperature Indicator

38.5. Register Summary - Temperature Indicator

39. ZCD - Zero-Cross Detection Module

39.1. External Resistor Selection

39.2. ZCD Logic Output

39.3. ZCD Logic Polarity

39.4. ZCD Interrupts

39.5. Correction for ZCPINV Offset

39.5.1. Correction by AC Coupling

39.5.2. Correction by Offset Current

39.6. Handling VPEAK Variations

39.7. Operation During Sleep

39.8. Effects of a Reset

39.9. Disabling the ZCD Module

39.10. Register Definitions: ZCD Control

39.10.1. ZCDCON

39.11. Register Summary - ZCD

40. Charge Pump

40.1. Manually Enabled

40.2. Automatically Enabled

40.4. Charge Pump Oscillator

40.5. Charge Pump Threshold

40.6. Charge Pump Ready

40.7. Register Definitions: Charge Pump

40.8. Register Summary - Charge Pump

41. Instruction Set Summary

41.1. Read-Modify-Write Operations

41.2. Standard Instruction Set

41.2.1. Standard Instruction Set 

42. ICSP™ - In-Circuit Serial Programming™

42.1. High-Voltage Programming Entry Mode

42.2. Low-Voltage Programming Entry Mode

42.3. Common Programming Interfaces

43. Register Summary

44. Electrical Specifications

44.1. Absolute Maximum Ratings(†)

44.2. Standard Operating Conditions

44.3. DC Characteristics

44.3.1. Supply Voltage

44.3.2. Supply Current (IDD)(1,2)

44.3.3. Power-Down Current (IPD)(1,2,3)

44.3.4. I/O Ports

44.3.5. Memory Programming Specifications

44.3.6. Thermal Characteristics

44.4. AC Characteristics

44.4.1. External Clock/Oscillator Timing Requirements

44.4.2. Internal Oscillator Parameters(1)

44.4.3. I/O and CLKOUT Timing Specifications

44.4.4. Timer0 and Timer1 External Clock Requirements

44.4.5. Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications

44.4.6. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2)

44.4.7. Analog-to-Digital Converter (ADC) Conversion Timing Specifications

44.4.8. 8-Bit DAC Specifications

44.4.9. Comparator Specifications

44.4.10. Zero-Cross Detect (ZCD) Specifications

44.4.11. Fixed Voltage Reference (FVR) Specifications

44.4.12. Temperature Indicator Requirements

44.4.13. Capture/Compare/PWM Requirements (CCP)

44.4.14. EUSART Synchronous Transmission Requirements

44.4.15. EUSART Synchronous Receive Requirements

44.4.16. SPI Mode Requirements

44.4.17. I2C Bus Start/Stop Bits Requirements

44.4.18. I2C Bus Data Requirements

44.4.19. Configurable Logic Cell (CLC) Characteristics

45. DC and AC Characteristics Graphs and Tables

46. Packaging Information

46.1. Package Details

47. Appendix A: Revision History

48. Microchip Information

The Microchip Website

Product Change Notification Service

Customer Support

Product Identification System

Microchip Devices Code Protection Feature

Quality Management System

Worldwide Sales and Service