Power Up/Power Down Sequence

The power up and power down sequence for ATWINC15x0B is shown in the following figure.

Figure 1. ATWINC15x0B Power Up/Down Sequence
The following table lists the parameters for the timing.
Table 1. ATWINC15x0B Power Up/Power Down Sequence
Symbol Min. Max. Unit Description Condition
tA 0 ms VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO must not rise before VBATT.
tB 0 VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating.
tC 5 CHIP_EN rise to RESETN rise This delay is needed because XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating.
tA’ 0 VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO.
tB’ 0 CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously.
tC’ 0 RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously.